6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 04:56:49 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Use ELF64 format instead of ELF32

Browse Source 
Reviewers: arsenm, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10392

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240331 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-06-22 21:03:54 +00:00
parent 309f60c15a
commit 9e7f0c8e77
4 changed files with 17 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -127,11 +127,14 @@ bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
namespace {
class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
bool Is64Bit;
public:
ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) :
AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { }
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
return createAMDGPUELFObjectWriter(OS);
return createAMDGPUELFObjectWriter(Is64Bit, OS);
}
};
@ -140,5 +143,8 @@ public:
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU) {
return new ELFAMDGPUAsmBackend(T);
Triple TargetTriple(TT);
// Use 64-bit ELF for amdgcn
return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn);
}

10
lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
View File

@ -18,7 +18,7 @@ namespace {
class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
public:
AMDGPUELFObjectWriter();
AMDGPUELFObjectWriter(bool Is64Bit);
protected:
unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel) const override {
@ -30,10 +30,10 @@ protected:
} // End anonymous namespace
AMDGPUELFObjectWriter::AMDGPUELFObjectWriter()
: MCELFObjectTargetWriter(false, 0, ELF::EM_AMDGPU, false) { }
AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit)
: MCELFObjectTargetWriter(Is64Bit, 0, ELF::EM_AMDGPU, false) { }
MCObjectWriter *llvm::createAMDGPUELFObjectWriter(raw_pwrite_stream &OS) {
MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter();
MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS) {
MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter(Is64Bit);
return createELFObjectWriter(MOTW, OS, true);
}

3
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -46,7 +46,8 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
MCObjectWriter *createAMDGPUELFObjectWriter(raw_pwrite_stream &OS);
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
raw_pwrite_stream &OS);
} // namespace llvm
#define GET_REGINFO_ENUM

2
test/CodeGen/AMDGPU/elf.ll
View File

@ -8,7 +8,7 @@
; Test that we don't try to produce a COFF file on windows
; RUN: llc < %s -mtriple=amdgcn-pc-mingw -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s -symbols -file-headers - | FileCheck --check-prefix=ELF %s
; ELF: Format: ELF32
; ELF: Format: ELF64
; ELF: Machine: EM_AMDGPU (0xE0)
; ELF: Name: .AMDGPU.config
; ELF: Type: SHT_PROGBITS