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Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4228,6 +4228,34 @@ static SDValue PerformVMOVRRDCombine(SDNode *N,
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return SDValue();
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}
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/// PerformVDUPLANECombine - Target-specific dag combine xforms for
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/// ARMISD::VDUPLANE.
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static SDValue PerformVDUPLANECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// If the source is already a VMOVIMM splat, the VDUPLANE is redundant.
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SDValue Op = N->getOperand(0);
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EVT VT = N->getValueType(0);
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// Ignore bit_converts.
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while (Op.getOpcode() == ISD::BIT_CONVERT)
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Op = Op.getOperand(0);
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if (Op.getOpcode() != ARMISD::VMOVIMM)
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return SDValue();
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// Make sure the VMOV element size is not bigger than the VDUPLANE elements.
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unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
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// The canonical VMOV for a zero vector uses a 32-bit element size.
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unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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unsigned EltBits;
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if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
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EltSize = 8;
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if (EltSize > VT.getVectorElementType().getSizeInBits())
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return SDValue();
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SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
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return DCI.CombineTo(N, Res, false);
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}
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/// getVShiftImm - Check if this is a valid build_vector for the immediate
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/// operand of a vector shift operation, where all the elements of the
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/// build_vector must have the same constant integer value.
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@ -4606,6 +4634,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SUB: return PerformSUBCombine(N, DCI);
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case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
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case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
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case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
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case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
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case ISD::SHL:
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case ISD::SRA:
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@ -267,3 +267,15 @@ entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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}
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; Radar 7373643
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;CHECK: redundantVdup:
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;CHECK: vmov.i8
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;CHECK-NOT: vdup.8
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;CHECK: vstr.64
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define void @redundantVdup(<8 x i8>* %ptr) nounwind {
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%1 = insertelement <8 x i8> undef, i8 -128, i32 0
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%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
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store <8 x i8> %2, <8 x i8>* %ptr, align 8
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ret void
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}
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