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Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.

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Radar 7373643.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-07-14 01:22:12 +00:00
parent a10b8494a5
commit 9e82bf12a0
2 changed files with 41 additions and 0 deletions
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29
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4228,6 +4228,34 @@ static SDValue PerformVMOVRRDCombine(SDNode *N,
return SDValue();
}
/// PerformVDUPLANECombine - Target-specific dag combine xforms for
/// ARMISD::VDUPLANE.
static SDValue PerformVDUPLANECombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
// If the source is already a VMOVIMM splat, the VDUPLANE is redundant.
SDValue Op = N->getOperand(0);
EVT VT = N->getValueType(0);
// Ignore bit_converts.
while (Op.getOpcode() == ISD::BIT_CONVERT)
Op = Op.getOperand(0);
if (Op.getOpcode() != ARMISD::VMOVIMM)
return SDValue();
// Make sure the VMOV element size is not bigger than the VDUPLANE elements.
unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
// The canonical VMOV for a zero vector uses a 32-bit element size.
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned EltBits;
if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
EltSize = 8;
if (EltSize > VT.getVectorElementType().getSizeInBits())
return SDValue();
SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
return DCI.CombineTo(N, Res, false);
}
/// getVShiftImm - Check if this is a valid build_vector for the immediate
/// operand of a vector shift operation, where all the elements of the
/// build_vector must have the same constant integer value.
@ -4606,6 +4634,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SUB: return PerformSUBCombine(N, DCI);
case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
case ISD::SHL:
case ISD::SRA:

12
test/CodeGen/ARM/vdup.ll
View File

@ -267,3 +267,15 @@ entry:
%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
ret <2 x double> %0
}
; Radar 7373643
;CHECK: redundantVdup:
;CHECK: vmov.i8
;CHECK-NOT: vdup.8
;CHECK: vstr.64
define void @redundantVdup(<8 x i8>* %ptr) nounwind {
%1 = insertelement <8 x i8> undef, i8 -128, i32 0
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
store <8 x i8> %2, <8 x i8>* %ptr, align 8
ret void
}