mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-28 02:24:53 +00:00
smarter loads and stores. can now handle base+offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
0bc68a87e7
commit
9e8d1094f2
@ -296,9 +296,34 @@ namespace {
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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void Select(SDOperand N);
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void Select(SDOperand N);
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void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
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};
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};
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}
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}
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//Check to see if the load is a constant offset from a base register
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void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
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{
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unsigned opcode = N.getOpcode();
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if (opcode == ISD::ADD) {
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if(N.getOperand(1).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
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{ //Normal imm add
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Reg = SelectExpr(N.getOperand(0));
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offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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return;
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}
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else if(N.getOperand(0).getOpcode() == ISD::Constant && cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 32767)
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{
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Reg = SelectExpr(N.getOperand(1));
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offset = cast<ConstantSDNode>(N.getOperand(0))->getValue();
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return;
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}
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}
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Reg = SelectExpr(N);
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offset = 0;
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return;
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}
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unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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{
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{
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unsigned Tmp1, Tmp2, Tmp3;
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unsigned Tmp1, Tmp2, Tmp3;
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@ -373,10 +398,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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SDOperand Chain = N.getOperand(0);
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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Select(Chain);
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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Opc = DestType == MVT::f64 ? Alpha::LDT_SYM : Alpha::LDS_SYM;
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Opc = DestType == MVT::f64 ? Alpha::LDT_SYM : Alpha::LDS_SYM;
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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@ -388,10 +413,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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}
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}
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else
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else
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{
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{
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Select(Chain);
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long offset;
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Tmp2 = SelectExpr(Address);
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SelectAddr(Address, Tmp1, offset);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp2);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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}
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return Result;
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return Result;
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}
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}
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@ -423,6 +448,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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return Result;
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return Result;
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case ISD::EXTLOAD:
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case ISD::EXTLOAD:
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{
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//include a conversion sequence for float loads to double
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//include a conversion sequence for float loads to double
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if (Result != notIn)
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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@ -434,18 +460,30 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 && "EXTLOAD not from f32");
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 && "EXTLOAD not from f32");
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assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
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assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1))) {
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDS_SYM, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
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{
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDS_SYM, 1, Tmp2).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Alpha::LDS_SYM, 1, Tmp2).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
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}
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else
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{
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long offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Alpha::LDS, 1, Tmp2).addImm(offset).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
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}
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return Result;
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return Result;
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}
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}
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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BuildMI(BB, Alpha::LDS, 1, Tmp2).addReg(Tmp1);
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp2);
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return Result;
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case ISD::UINT_TO_FP:
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case ISD::UINT_TO_FP:
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case ISD::SINT_TO_FP:
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case ISD::SINT_TO_FP:
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@ -521,7 +559,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::ConstantPool:
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case ISD::ConstantPool:
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Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LOAD, 1, Result).addConstantPoolIndex(Tmp1);
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BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
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return Result;
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return Result;
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case ISD::FrameIndex:
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case ISD::FrameIndex:
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@ -530,14 +568,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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return Result;
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case ISD::EXTLOAD:
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case ISD::EXTLOAD:
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{
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// Make sure we generate both values.
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// Make sure we generate both values.
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if (Result != notIn)
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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SDOperand Chain = N.getOperand(0);
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Tmp1 = SelectExpr(Node->getOperand(1));
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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switch(Node->getValueType(0)) {
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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@ -546,75 +586,111 @@ unsigned ISel::SelectExpr(SDOperand N) {
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default:
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default:
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Node->dump();
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Node->dump();
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assert(0 && "Bad extend load!");
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assert(0 && "Bad extend load!");
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case MVT::i64:
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case MVT::i64: Opc = Alpha::LDQ; break;
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BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp1);
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case MVT::i32: Opc = Alpha::LDL; break;
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break;
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case MVT::i16: Opc = Alpha::LDWU; break;
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8:
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case MVT::i8: Opc = Alpha::LDBU; break;
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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}
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break;
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address))
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{
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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else
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{
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long offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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}
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return Result;
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return Result;
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}
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case ISD::SEXTLOAD:
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case ISD::SEXTLOAD:
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{
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// Make sure we generate both values.
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// Make sure we generate both values.
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if (Result != notIn)
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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SDOperand Chain = N.getOperand(0);
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Tmp1 = SelectExpr(Node->getOperand(1));
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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switch(Node->getValueType(0)) {
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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default: Node->dump(); assert(0 && "Bad sign extend!");
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Node->dump();
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case MVT::i32: Opc = Alpha::LDL; break;
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assert(0 && "Bad sign extend!");
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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}
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break;
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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else
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{
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long offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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}
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return Result;
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return Result;
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}
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case ISD::ZEXTLOAD:
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case ISD::ZEXTLOAD:
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{
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// Make sure we generate both values.
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// Make sure we generate both values.
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if (Result != notIn)
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Select(Node->getOperand(0)); // chain
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SDOperand Chain = N.getOperand(0);
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Tmp1 = SelectExpr(Node->getOperand(1));
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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switch(Node->getValueType(0)) {
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to zero extend to.");
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default: Node->dump(); assert(0 && "Unknown type to zero extend to.");
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case MVT::i64:
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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default: Node->dump(); assert(0 && "Bad sign extend!");
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Node->dump();
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case MVT::i16: Opc = Alpha::LDWU; break;
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assert(0 && "Bad sign extend!");
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case MVT::i8: Opc = Alpha::LDBU; break;
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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case MVT::i8:
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BuildMI(BB, Alpha::LDBU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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}
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}
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break;
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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else
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{
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long offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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}
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return Result;
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return Result;
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}
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case ISD::GlobalAddress:
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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@ -1107,7 +1183,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
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ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
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unsigned CPI = CP->getConstantPoolIndex(C);
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unsigned CPI = CP->getConstantPoolIndex(C);
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LOAD, 1, Result).addConstantPoolIndex(CPI);
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BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(CPI);
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}
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}
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return Result;
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return Result;
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}
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}
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@ -1122,24 +1198,24 @@ unsigned ISel::SelectExpr(SDOperand N) {
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SDOperand Chain = N.getOperand(0);
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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assert(N.getValue(0).getValueType() == MVT::i64 && "unknown Load dest type");
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assert(N.getValue(0).getValueType() == MVT::i64 && "unknown Load dest type");
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if (Address.getOpcode() == ISD::GlobalAddress)
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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{
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Select(Chain);
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LOAD, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LOAD, 1, Result).addConstantPoolIndex(CP->getIndex());
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BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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}
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else
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else
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{
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{
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Select(Chain);
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long offset;
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Tmp2 = SelectExpr(Address);
|
SelectAddr(Address, Tmp1, offset);
|
||||||
BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp2);
|
BuildMI(BB, Alpha::LDQ, 2, Result).addImm(offset).addReg(Tmp1);
|
||||||
}
|
}
|
||||||
return Result;
|
return Result;
|
||||||
}
|
}
|
||||||
@ -1243,35 +1319,36 @@ void ISel::Select(SDOperand N) {
|
|||||||
|
|
||||||
case ISD::STORE:
|
case ISD::STORE:
|
||||||
{
|
{
|
||||||
Select(N.getOperand(0));
|
SDOperand Chain = N.getOperand(0);
|
||||||
Tmp1 = SelectExpr(N.getOperand(1)); //value
|
SDOperand Value = N.getOperand(1);
|
||||||
MVT::ValueType DestType = N.getOperand(1).getValueType();
|
SDOperand Address = N.getOperand(2);
|
||||||
if (N.getOperand(2).getOpcode() == ISD::GlobalAddress)
|
Select(Chain);
|
||||||
|
|
||||||
|
Tmp1 = SelectExpr(Value); //value
|
||||||
|
MVT::ValueType DestType = Value.getValueType();
|
||||||
|
|
||||||
|
if (Address.getOpcode() == ISD::GlobalAddress)
|
||||||
{
|
{
|
||||||
AlphaLowering.restoreGP(BB);
|
AlphaLowering.restoreGP(BB);
|
||||||
if (DestType == MVT::i64) Opc = Alpha::STORE;
|
switch(DestType) {
|
||||||
else if (DestType == MVT::f64) Opc = Alpha::STT_SYM;
|
default: assert(0 && "unknown Type in store");
|
||||||
else if (DestType == MVT::f32) Opc = Alpha::STS_SYM;
|
case MVT::i64: Opc = Alpha::STQ_SYM; break;
|
||||||
else assert(0 && "unknown Type in store");
|
case MVT::f64: Opc = Alpha::STT_SYM; break;
|
||||||
BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(N.getOperand(2))->getGlobal());
|
case MVT::f32: Opc = Alpha::STS_SYM; break;
|
||||||
}
|
}
|
||||||
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(2)))
|
BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
|
||||||
{
|
|
||||||
AlphaLowering.restoreGP(BB);
|
|
||||||
if (DestType == MVT::i64) Opc = Alpha::STORE;
|
|
||||||
else if (DestType == MVT::f64) Opc = Alpha::STT_SYM;
|
|
||||||
else if (DestType == MVT::f32) Opc = Alpha::STS_SYM;
|
|
||||||
else assert(0 && "unknown Type in store");
|
|
||||||
BuildMI(BB, Opc, 2).addReg(Tmp1).addConstantPoolIndex(CP->getIndex());
|
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
Tmp2 = SelectExpr(N.getOperand(2)); //address
|
switch(DestType) {
|
||||||
if (DestType == MVT::i64) Opc = Alpha::STQ;
|
default: assert(0 && "unknown Type in store");
|
||||||
else if (DestType == MVT::f64) Opc = Alpha::STT;
|
case MVT::i64: Opc = Alpha::STQ; break;
|
||||||
else if (DestType == MVT::f32) Opc = Alpha::STS;
|
case MVT::f64: Opc = Alpha::STT; break;
|
||||||
else assert(0 && "unknown Type in store");
|
case MVT::f32: Opc = Alpha::STS; break;
|
||||||
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
|
}
|
||||||
|
long offset;
|
||||||
|
SelectAddr(Address, Tmp2, offset);
|
||||||
|
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -1288,26 +1365,42 @@ void ISel::Select(SDOperand N) {
|
|||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
||||||
case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
|
case ISD::TRUNCSTORE:
|
||||||
MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
|
{
|
||||||
if (StoredTy == MVT::i64) {
|
SDOperand Chain = N.getOperand(0);
|
||||||
Node->dump();
|
SDOperand Value = N.getOperand(1);
|
||||||
assert(StoredTy != MVT::i64 && "Unsupported TRUNCSTORE for this target!");
|
SDOperand Address = N.getOperand(2);
|
||||||
}
|
Select(Chain);
|
||||||
|
|
||||||
Select(N.getOperand(0));
|
MVT::ValueType DestType = cast<MVTSDNode>(Node)->getExtraValueType();
|
||||||
Tmp1 = SelectExpr(N.getOperand(1));
|
|
||||||
Tmp2 = SelectExpr(N.getOperand(2));
|
|
||||||
|
|
||||||
switch (StoredTy) {
|
Tmp1 = SelectExpr(Value); //value
|
||||||
default: Node->dump(); assert(0 && "Unhandled Type");
|
|
||||||
|
if (Address.getOpcode() == ISD::GlobalAddress)
|
||||||
|
{
|
||||||
|
AlphaLowering.restoreGP(BB);
|
||||||
|
switch(DestType) {
|
||||||
|
default: assert(0 && "unknown Type in store");
|
||||||
case MVT::i1: //FIXME: DAG does not promote this load
|
case MVT::i1: //FIXME: DAG does not promote this load
|
||||||
case MVT::i8: Opc = Alpha::STB; break;
|
case MVT::i8: Opc = Alpha::STB; break;
|
||||||
case MVT::i16: Opc = Alpha::STW; break;
|
case MVT::i16: Opc = Alpha::STW; break;
|
||||||
case MVT::i32: Opc = Alpha::STL; break;
|
case MVT::i32: Opc = Alpha::STL; break;
|
||||||
}
|
}
|
||||||
|
BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
|
||||||
BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(0).addReg(Tmp2);
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
switch(DestType) {
|
||||||
|
default: assert(0 && "unknown Type in store");
|
||||||
|
case MVT::i1: //FIXME: DAG does not promote this load
|
||||||
|
case MVT::i8: Opc = Alpha::STB; break;
|
||||||
|
case MVT::i16: Opc = Alpha::STW; break;
|
||||||
|
case MVT::i32: Opc = Alpha::STL; break;
|
||||||
|
}
|
||||||
|
long offset;
|
||||||
|
SelectAddr(Address, Tmp2, offset);
|
||||||
|
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
||||||
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -57,13 +57,18 @@ let Uses = [R28] in
|
|||||||
def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword
|
def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword
|
||||||
|
|
||||||
let Uses = [R29, R28] in {
|
let Uses = [R29, R28] in {
|
||||||
def STORE : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stq $RA,$DISP">; //Store quadword
|
|
||||||
def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
|
def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
|
||||||
def LOAD : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
|
def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
|
||||||
def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
|
def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
|
||||||
def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
|
def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
|
||||||
def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
|
def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
|
||||||
def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
|
def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
|
||||||
|
|
||||||
|
def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
|
||||||
|
def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
|
||||||
|
def STL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stl $RA,$DISP">; // Store longword
|
||||||
|
def STQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stq $RA,$DISP">; //Store quadword
|
||||||
|
|
||||||
def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float
|
def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float
|
||||||
def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
|
def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user