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Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2012-03-05 05:37:41 +00:00
parent ec93b6deca
commit 9ebfbf8b9f
21 changed files with 80 additions and 80 deletions
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8
lib/Target/Hexagon/HexagonFrameLowering.cpp
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@@ -235,7 +235,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters(
//
// Check if we can use a double-word store.
//
const unsigned* SuperReg = TRI->getSuperRegisters(Reg);
const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
// Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
@@ -243,7 +243,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters(
const TargetRegisterClass* SuperRegClass = 0;
if (ContiguousRegs && (i < CSI.size()-1)) {
const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
assert(SuperRegNext[0] && !SuperRegNext[1] &&
"Expected exactly one superreg");
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
@@ -295,14 +295,14 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters(
//
// Check if we can use a double-word load.
//
const unsigned* SuperReg = TRI->getSuperRegisters(Reg);
const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
const TargetRegisterClass* SuperRegClass = 0;
// Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
bool CanUseDblLoad = false;
if (ContiguousRegs && (i < CSI.size()-1)) {
const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
assert(SuperRegNext[0] && !SuperRegNext[1] &&
"Expected exactly one superreg");
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);