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Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-03-05 05:37:41 +00:00
parent ec93b6deca
commit 9ebfbf8b9f
21 changed files with 80 additions and 80 deletions
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18
include/llvm/MC/MCRegisterInfo.h
View File

@ -107,9 +107,9 @@ public:
/// ///
struct MCRegisterDesc { struct MCRegisterDesc {
const char *Name; // Printable name for the reg (for debugging) const char *Name; // Printable name for the reg (for debugging)
unsigned Overlaps; // Overlapping registers, described above uint16_t Overlaps; // Overlapping registers, described above
unsigned SubRegs; // Sub-register set, described above uint16_t SubRegs; // Sub-register set, described above
unsigned SuperRegs; // Super-register set, described above uint16_t SuperRegs; // Super-register set, described above
}; };
/// MCRegisterInfo base class - We assume that the target defines a static /// MCRegisterInfo base class - We assume that the target defines a static
@ -134,8 +134,8 @@ private:
const MCRegisterClass *Classes; // Pointer to the regclass array const MCRegisterClass *Classes; // Pointer to the regclass array
unsigned NumClasses; // Number of entries in the array unsigned NumClasses; // Number of entries in the array
const uint16_t *Overlaps; // Pointer to the overlaps array const uint16_t *Overlaps; // Pointer to the overlaps array
const unsigned *SubRegs; // Pointer to the subregs array const uint16_t *SubRegs; // Pointer to the subregs array
const unsigned *SuperRegs; // Pointer to the superregs array const uint16_t *SuperRegs; // Pointer to the superregs array
const uint16_t *SubRegIndices; // Pointer to the subreg lookup const uint16_t *SubRegIndices; // Pointer to the subreg lookup
// array. // array.
unsigned NumSubRegIndices; // Number of subreg indices. unsigned NumSubRegIndices; // Number of subreg indices.
@ -150,8 +150,8 @@ public:
/// auto-generated routines. *DO NOT USE*. /// auto-generated routines. *DO NOT USE*.
void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
const MCRegisterClass *C, unsigned NC, const MCRegisterClass *C, unsigned NC,
const uint16_t *O, const unsigned *Sub, const uint16_t *O, const uint16_t *Sub,
const unsigned *Super, const uint16_t *Super,
const uint16_t *SubIndices, const uint16_t *SubIndices,
unsigned NumIndices) { unsigned NumIndices) {
Desc = D; Desc = D;
@ -237,7 +237,7 @@ public:
/// returned is zero terminated and sorted according to super-sub register /// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
/// ///
const unsigned *getSubRegisters(unsigned RegNo) const { const uint16_t *getSubRegisters(unsigned RegNo) const {
return SubRegs + get(RegNo).SubRegs; return SubRegs + get(RegNo).SubRegs;
} }
@ -263,7 +263,7 @@ public:
/// returned is zero terminated and sorted according to super-sub register /// returned is zero terminated and sorted according to super-sub register
/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
/// ///
const unsigned *getSuperRegisters(unsigned RegNo) const { const uint16_t *getSuperRegisters(unsigned RegNo) const {
return SuperRegs + get(RegNo).SuperRegs; return SuperRegs + get(RegNo).SuperRegs;
} }

6
include/llvm/Target/TargetRegisterInfo.h
View File

@ -159,7 +159,7 @@ public:
/// getSubClassMask - Returns a bit vector of subclasses, including this one. /// getSubClassMask - Returns a bit vector of subclasses, including this one.
/// The vector is indexed by class IDs, see hasSubClassEq() above for how to /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
/// use it. /// use it.
const unsigned *getSubClassMask() const { const uint32_t *getSubClassMask() const {
return SubClassMask; return SubClassMask;
} }
@ -340,7 +340,7 @@ public:
/// isSuperRegister - Returns true if regB is a super-register of regA. /// isSuperRegister - Returns true if regB is a super-register of regA.
/// ///
bool isSuperRegister(unsigned regA, unsigned regB) const { bool isSuperRegister(unsigned regA, unsigned regB) const {
for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regList){
if (*regList == regB) return true; if (*regList == regB) return true;
} }
return false; return false;
@ -387,7 +387,7 @@ public:
/// Reg so its sub-register of index SubIdx is Reg. /// Reg so its sub-register of index SubIdx is Reg.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
return SR; return SR;
return 0; return 0;

4
lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -265,7 +265,7 @@ void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
IsImplicitDefUse(MI, MO)) { IsImplicitDefUse(MI, MO)) {
const unsigned Reg = MO.getReg(); const unsigned Reg = MO.getReg();
PassthruRegs.insert(Reg); PassthruRegs.insert(Reg);
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) { *Subreg; ++Subreg) {
PassthruRegs.insert(*Subreg); PassthruRegs.insert(*Subreg);
} }
@ -333,7 +333,7 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
} }
// Repeat for subregisters. // Repeat for subregisters.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) { *Subreg; ++Subreg) {
unsigned SubregReg = *Subreg; unsigned SubregReg = *Subreg;
if (!State->IsLive(SubregReg)) { if (!State->IsLive(SubregReg)) {

2
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -798,7 +798,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
for (const unsigned *SR = TRI->getSuperRegisters(MLoc.getReg()); for (const uint16_t *SR = TRI->getSuperRegisters(MLoc.getReg());
*SR && Reg < 0; ++SR) { *SR && Reg < 0; ++SR) {
Reg = TRI->getDwarfRegNum(*SR, false); Reg = TRI->getDwarfRegNum(*SR, false);
// FIXME: Get the bit range this register uses of the superregister // FIXME: Get the bit range this register uses of the superregister

4
lib/CodeGen/BranchFolding.cpp
View File

@ -136,7 +136,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
break; break;
unsigned Reg = I->getOperand(0).getReg(); unsigned Reg = I->getOperand(0).getReg();
ImpDefRegs.insert(Reg); ImpDefRegs.insert(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) unsigned SubReg = *SubRegs; ++SubRegs)
ImpDefRegs.insert(SubReg); ImpDefRegs.insert(SubReg);
++I; ++I;
@ -1521,7 +1521,7 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
} else { } else {
if (Uses.count(Reg)) { if (Uses.count(Reg)) {
Uses.erase(Reg); Uses.erase(Reg);
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
Uses.erase(*SR); // Use getSubRegisters to be conservative Uses.erase(*SR); // Use getSubRegisters to be conservative
} }
Defs.insert(Reg); Defs.insert(Reg);

6
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -234,7 +234,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
if (MO.isUse() && Special) { if (MO.isUse() && Special) {
if (KeepRegs.insert(Reg)) { if (KeepRegs.insert(Reg)) {
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
KeepRegs.insert(*Subreg); KeepRegs.insert(*Subreg);
} }
@ -280,7 +280,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
Classes[Reg] = 0; Classes[Reg] = 0;
RegRefs.erase(Reg); RegRefs.erase(Reg);
// Repeat, for all subregs. // Repeat, for all subregs.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) { *Subreg; ++Subreg) {
unsigned SubregReg = *Subreg; unsigned SubregReg = *Subreg;
DefIndices[SubregReg] = Count; DefIndices[SubregReg] = Count;
@ -290,7 +290,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
RegRefs.erase(SubregReg); RegRefs.erase(SubregReg);
} }
// Conservatively mark super-registers as unusable. // Conservatively mark super-registers as unusable.
for (const unsigned *Super = TRI->getSuperRegisters(Reg); for (const uint16_t *Super = TRI->getSuperRegisters(Reg);
*Super; ++Super) { *Super; ++Super) {
unsigned SuperReg = *Super; unsigned SuperReg = *Super;
Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);

2
lib/CodeGen/DeadMachineInstructionElim.cpp
View File

@ -171,7 +171,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
// Check the subreg set, not the alias set, because a def // Check the subreg set, not the alias set, because a def
// of a super-register may still be partially live after // of a super-register may still be partially live after
// this def. // this def.
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
*SubRegs; ++SubRegs) *SubRegs; ++SubRegs)
LivePhysRegs.reset(*SubRegs); LivePhysRegs.reset(*SubRegs);
} }

10
lib/CodeGen/IfConversion.cpp
View File

@ -962,7 +962,7 @@ static void InitPredRedefs(MachineBasicBlock *BB, SmallSet<unsigned,4> &Redefs,
E = BB->livein_end(); I != E; ++I) { E = BB->livein_end(); I != E; ++I) {
unsigned Reg = *I; unsigned Reg = *I;
Redefs.insert(Reg); Redefs.insert(Reg);
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
Redefs.insert(*Subreg); Redefs.insert(*Subreg);
} }
@ -983,7 +983,7 @@ static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
Defs.push_back(Reg); Defs.push_back(Reg);
else if (MO.isKill()) { else if (MO.isKill()) {
Redefs.erase(Reg); Redefs.erase(Reg);
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
Redefs.erase(*SR); Redefs.erase(*SR);
} }
} }
@ -996,7 +996,7 @@ static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
true/*IsImp*/,false/*IsKill*/)); true/*IsImp*/,false/*IsKill*/));
} else { } else {
Redefs.insert(Reg); Redefs.insert(Reg);
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
Redefs.insert(*SR); Redefs.insert(*SR);
} }
} }
@ -1335,7 +1335,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// These are defined before ctrl flow reach the 'false' instructions. // These are defined before ctrl flow reach the 'false' instructions.
// They cannot be modified by the 'true' instructions. // They cannot be modified by the 'true' instructions.
ExtUses.insert(Reg); ExtUses.insert(Reg);
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
ExtUses.insert(*SR); ExtUses.insert(*SR);
} }
} }
@ -1344,7 +1344,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
unsigned Reg = Defs[i]; unsigned Reg = Defs[i];
if (!ExtUses.count(Reg)) { if (!ExtUses.count(Reg)) {
RedefsByFalse.insert(Reg); RedefsByFalse.insert(Reg);
for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
RedefsByFalse.insert(*SR); RedefsByFalse.insert(*SR);
} }
} }

34
lib/CodeGen/LiveVariables.cpp
View File

@ -191,7 +191,7 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
unsigned LastDefReg = 0; unsigned LastDefReg = 0;
unsigned LastDefDist = 0; unsigned LastDefDist = 0;
MachineInstr *LastDef = NULL; MachineInstr *LastDef = NULL;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
MachineInstr *Def = PhysRegDef[SubReg]; MachineInstr *Def = PhysRegDef[SubReg];
if (!Def) if (!Def)
@ -215,7 +215,7 @@ MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
unsigned DefReg = MO.getReg(); unsigned DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) { if (TRI->isSubRegister(Reg, DefReg)) {
PartDefRegs.insert(DefReg); PartDefRegs.insert(DefReg);
for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg); for (const uint16_t *SubRegs = TRI->getSubRegisters(DefReg);
unsigned SubReg = *SubRegs; ++SubRegs) unsigned SubReg = *SubRegs; ++SubRegs)
PartDefRegs.insert(SubReg); PartDefRegs.insert(SubReg);
} }
@ -246,7 +246,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
true/*IsImp*/)); true/*IsImp*/));
PhysRegDef[Reg] = LastPartialDef; PhysRegDef[Reg] = LastPartialDef;
SmallSet<unsigned, 8> Processed; SmallSet<unsigned, 8> Processed;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
if (Processed.count(SubReg)) if (Processed.count(SubReg))
continue; continue;
@ -258,7 +258,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
false/*IsDef*/, false/*IsDef*/,
true/*IsImp*/)); true/*IsImp*/));
PhysRegDef[SubReg] = LastPartialDef; PhysRegDef[SubReg] = LastPartialDef;
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
Processed.insert(*SS); Processed.insert(*SS);
} }
} }
@ -270,7 +270,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
// Remember this use. // Remember this use.
PhysRegUse[Reg] = MI; PhysRegUse[Reg] = MI;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) unsigned SubReg = *SubRegs; ++SubRegs)
PhysRegUse[SubReg] = MI; PhysRegUse[SubReg] = MI;
} }
@ -286,7 +286,7 @@ MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef; MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef]; unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
unsigned LastPartDefDist = 0; unsigned LastPartDefDist = 0;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
MachineInstr *Def = PhysRegDef[SubReg]; MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) { if (Def && Def != LastDef) {
@ -335,7 +335,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
MachineInstr *LastPartDef = 0; MachineInstr *LastPartDef = 0;
unsigned LastPartDefDist = 0; unsigned LastPartDefDist = 0;
SmallSet<unsigned, 8> PartUses; SmallSet<unsigned, 8> PartUses;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
MachineInstr *Def = PhysRegDef[SubReg]; MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) { if (Def && Def != LastDef) {
@ -350,7 +350,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
} }
if (MachineInstr *Use = PhysRegUse[SubReg]) { if (MachineInstr *Use = PhysRegUse[SubReg]) {
PartUses.insert(SubReg); PartUses.insert(SubReg);
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
PartUses.insert(*SS); PartUses.insert(*SS);
unsigned Dist = DistanceMap[Use]; unsigned Dist = DistanceMap[Use];
if (Dist > LastRefOrPartRefDist) { if (Dist > LastRefOrPartRefDist) {
@ -366,7 +366,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
// EAX<dead> = op AL<imp-def> // EAX<dead> = op AL<imp-def>
// That is, EAX def is dead but AL def extends pass it. // That is, EAX def is dead but AL def extends pass it.
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
if (!PartUses.count(SubReg)) if (!PartUses.count(SubReg))
continue; continue;
@ -387,11 +387,11 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
else { else {
LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true); LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
PhysRegUse[SubReg] = LastRefOrPartRef; PhysRegUse[SubReg] = LastRefOrPartRef;
for (const unsigned *SSRegs = TRI->getSubRegisters(SubReg); for (const uint16_t *SSRegs = TRI->getSubRegisters(SubReg);
unsigned SSReg = *SSRegs; ++SSRegs) unsigned SSReg = *SSRegs; ++SSRegs)
PhysRegUse[SSReg] = LastRefOrPartRef; PhysRegUse[SSReg] = LastRefOrPartRef;
} }
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
PartUses.erase(*SS); PartUses.erase(*SS);
} }
} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) { } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
@ -433,7 +433,7 @@ void LiveVariables::HandleRegMask(const MachineOperand &MO) {
// Kill the largest clobbered super-register. // Kill the largest clobbered super-register.
// This avoids needless implicit operands. // This avoids needless implicit operands.
unsigned Super = Reg; unsigned Super = Reg;
for (const unsigned *SR = TRI->getSuperRegisters(Reg); *SR; ++SR) for (const uint16_t *SR = TRI->getSuperRegisters(Reg); *SR; ++SR)
if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR)) if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
Super = *SR; Super = *SR;
HandlePhysRegKill(Super, 0); HandlePhysRegKill(Super, 0);
@ -446,10 +446,10 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
SmallSet<unsigned, 32> Live; SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] || PhysRegUse[Reg]) { if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
Live.insert(Reg); Live.insert(Reg);
for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
Live.insert(*SS); Live.insert(*SS);
} else { } else {
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
// If a register isn't itself defined, but all parts that make up of it // If a register isn't itself defined, but all parts that make up of it
// are defined, then consider it also defined. // are defined, then consider it also defined.
@ -461,7 +461,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
continue; continue;
if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
Live.insert(SubReg); Live.insert(SubReg);
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
Live.insert(*SS); Live.insert(*SS);
} }
} }
@ -471,7 +471,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
// is referenced. // is referenced.
HandlePhysRegKill(Reg, MI); HandlePhysRegKill(Reg, MI);
// Only some of the sub-registers are used. // Only some of the sub-registers are used.
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
if (!Live.count(SubReg)) if (!Live.count(SubReg))
// Skip if this sub-register isn't defined. // Skip if this sub-register isn't defined.
@ -490,7 +490,7 @@ void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
Defs.pop_back(); Defs.pop_back();
PhysRegDef[Reg] = MI; PhysRegDef[Reg] = MI;
PhysRegUse[Reg] = NULL; PhysRegUse[Reg] = NULL;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
PhysRegDef[SubReg] = MI; PhysRegDef[SubReg] = MI;
PhysRegUse[SubReg] = NULL; PhysRegUse[SubReg] = NULL;

6
lib/CodeGen/MachineCopyPropagation.cpp
View File

@ -64,7 +64,7 @@ MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
unsigned MappedDef = SI->second; unsigned MappedDef = SI->second;
// Source of copy is no longer available for propagation. // Source of copy is no longer available for propagation.
if (AvailCopyMap.erase(MappedDef)) { if (AvailCopyMap.erase(MappedDef)) {
for (const unsigned *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
AvailCopyMap.erase(*SR); AvailCopyMap.erase(*SR);
} }
} }
@ -73,7 +73,7 @@ MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg,
if (SI != SrcMap.end()) { if (SI != SrcMap.end()) {
unsigned MappedDef = SI->second; unsigned MappedDef = SI->second;
if (AvailCopyMap.erase(MappedDef)) { if (AvailCopyMap.erase(MappedDef)) {
for (const unsigned *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR) for (const uint16_t *SR = TRI->getSubRegisters(MappedDef); *SR; ++SR)
AvailCopyMap.erase(*SR); AvailCopyMap.erase(*SR);
} }
} }
@ -206,7 +206,7 @@ bool MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
} }
CopyMap[Def] = MI; CopyMap[Def] = MI;
AvailCopyMap[Def] = MI; AvailCopyMap[Def] = MI;
for (const unsigned *SR = TRI->getSubRegisters(Def); *SR; ++SR) { for (const uint16_t *SR = TRI->getSubRegisters(Def); *SR; ++SR) {
CopyMap[*SR] = MI; CopyMap[*SR] = MI;
AvailCopyMap[*SR] = MI; AvailCopyMap[*SR] = MI;
} }

2
lib/CodeGen/MachineInstrBundle.cpp
View File

@ -169,7 +169,7 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
} }
if (!MO.isDead()) { if (!MO.isDead()) {
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) { unsigned SubReg = *SubRegs; ++SubRegs) {
if (LocalDefSet.insert(SubReg)) if (LocalDefSet.insert(SubReg))
LocalDefs.push_back(SubReg); LocalDefs.push_back(SubReg);

8
lib/CodeGen/MachineVerifier.cpp
View File

@ -89,7 +89,7 @@ namespace {
void addRegWithSubRegs(RegVector &RV, unsigned Reg) { void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
RV.push_back(Reg); RV.push_back(Reg);
if (TargetRegisterInfo::isPhysicalRegister(Reg)) if (TargetRegisterInfo::isPhysicalRegister(Reg))
for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++)
RV.push_back(*R); RV.push_back(*R);
} }
@ -383,7 +383,7 @@ void MachineVerifier::visitMachineFunctionBefore() {
// A sub-register of a reserved register is also reserved // A sub-register of a reserved register is also reserved
for (int Reg = regsReserved.find_first(); Reg>=0; for (int Reg = regsReserved.find_first(); Reg>=0;
Reg = regsReserved.find_next(Reg)) { Reg = regsReserved.find_next(Reg)) {
for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) { for (const uint16_t *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
// FIXME: This should probably be: // FIXME: This should probably be:
// assert(regsReserved.test(*Sub) && "Non-reserved sub-register"); // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
regsReserved.set(*Sub); regsReserved.set(*Sub);
@ -553,7 +553,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
continue; continue;
} }
regsLive.insert(*I); regsLive.insert(*I);
for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++) for (const uint16_t *R = TRI->getSubRegisters(*I); *R; R++)
regsLive.insert(*R); regsLive.insert(*R);
} }
regsLiveInButUnused = regsLive; regsLiveInButUnused = regsLive;
@ -563,7 +563,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
BitVector PR = MFI->getPristineRegs(MBB); BitVector PR = MFI->getPristineRegs(MBB);
for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
regsLive.insert(I); regsLive.insert(I);
for (const unsigned *R = TRI->getSubRegisters(I); *R; R++) for (const uint16_t *R = TRI->getSubRegisters(I); *R; R++)
regsLive.insert(*R); regsLive.insert(*R);
} }

12
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -377,7 +377,7 @@ void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
unsigned Reg = *I; unsigned Reg = *I;
LiveRegs.set(Reg); LiveRegs.set(Reg);
// Repeat, for all subregs. // Repeat, for all subregs.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
LiveRegs.set(*Subreg); LiveRegs.set(*Subreg);
} }
@ -391,7 +391,7 @@ void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
unsigned Reg = *I; unsigned Reg = *I;
LiveRegs.set(Reg); LiveRegs.set(Reg);
// Repeat, for all subregs. // Repeat, for all subregs.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
LiveRegs.set(*Subreg); LiveRegs.set(*Subreg);
} }
@ -418,7 +418,7 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
MO.setIsKill(false); MO.setIsKill(false);
bool AllDead = true; bool AllDead = true;
const unsigned SuperReg = MO.getReg(); const unsigned SuperReg = MO.getReg();
for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg); for (const uint16_t *Subreg = TRI->getSubRegisters(SuperReg);
*Subreg; ++Subreg) { *Subreg; ++Subreg) {
if (LiveRegs.test(*Subreg)) { if (LiveRegs.test(*Subreg)) {
MI->addOperand(MachineOperand::CreateReg(*Subreg, MI->addOperand(MachineOperand::CreateReg(*Subreg,
@ -471,7 +471,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
LiveRegs.reset(Reg); LiveRegs.reset(Reg);
// Repeat for all subregs. // Repeat for all subregs.
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
LiveRegs.reset(*Subreg); LiveRegs.reset(*Subreg);
} }
@ -490,7 +490,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
if (!killedRegs.test(Reg)) { if (!killedRegs.test(Reg)) {
kill = true; kill = true;
// A register is not killed if any subregs are live... // A register is not killed if any subregs are live...
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) { *Subreg; ++Subreg) {
if (LiveRegs.test(*Subreg)) { if (LiveRegs.test(*Subreg)) {
kill = false; kill = false;
@ -524,7 +524,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
LiveRegs.set(Reg); LiveRegs.set(Reg);
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
LiveRegs.set(*Subreg); LiveRegs.set(*Subreg);
} }

2
lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -113,7 +113,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
unsigned Reg = MI->getOperand(0).getReg(); unsigned Reg = MI->getOperand(0).getReg();
ImpDefRegs.insert(Reg); ImpDefRegs.insert(Reg);
if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS) for (const uint16_t *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
ImpDefRegs.insert(*SS); ImpDefRegs.insert(*SS);
} }
continue; continue;

6
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -490,7 +490,7 @@ bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP,
// If the IntB live range is assigned to a physical register, and if that // If the IntB live range is assigned to a physical register, and if that
// physreg has sub-registers, update their live intervals as well. // physreg has sub-registers, update their live intervals as well.
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
for (const unsigned *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) { for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
if (!LIS->hasInterval(*SR)) if (!LIS->hasInterval(*SR))
continue; continue;
LiveInterval &SRLI = LIS->getInterval(*SR); LiveInterval &SRLI = LIS->getInterval(*SR);
@ -974,7 +974,7 @@ static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
if (li.empty()) { if (li.empty()) {
if (TargetRegisterInfo::isPhysicalRegister(li.reg)) if (TargetRegisterInfo::isPhysicalRegister(li.reg))
for (const unsigned* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) { for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
if (!LIS->hasInterval(*SR)) if (!LIS->hasInterval(*SR))
continue; continue;
LiveInterval &sli = LIS->getInterval(*SR); LiveInterval &sli = LIS->getInterval(*SR);
@ -1936,7 +1936,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
// remain alive. // remain alive.
if (!TargetRegisterInfo::isPhysicalRegister(reg)) if (!TargetRegisterInfo::isPhysicalRegister(reg))
continue; continue;
for (const unsigned *SR = TRI->getSubRegisters(reg); for (const uint16_t *SR = TRI->getSubRegisters(reg);
unsigned S = *SR; ++SR) unsigned S = *SR; ++SR)
if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx)) if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
MI->addRegisterDefined(S, TRI); MI->addRegisterDefined(S, TRI);

6
lib/CodeGen/RegisterScavenging.cpp
View File

@ -37,7 +37,7 @@ using namespace llvm;
void RegScavenger::setUsed(unsigned Reg) { void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg); RegsAvailable.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.reset(SubReg); RegsAvailable.reset(SubReg);
} }
@ -109,7 +109,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
BV.set(Reg); BV.set(Reg);
for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++)
BV.set(*R); BV.set(*R);
} }
@ -190,7 +190,7 @@ void RegScavenger::forward() {
// Ideally we would like a way to model this, but leaving the // Ideally we would like a way to model this, but leaving the
// insert_subreg around causes both correctness and performance issues. // insert_subreg around causes both correctness and performance issues.
bool SubUsed = false; bool SubUsed = false;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) unsigned SubReg = *SubRegs; ++SubRegs)
if (isUsed(SubReg)) { if (isUsed(SubReg)) {
SubUsed = true; SubUsed = true;

4
lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -76,7 +76,7 @@ static void TrackDefUses(MachineInstr *MI,
for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) { for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
unsigned Reg = LocalUses[i]; unsigned Reg = LocalUses[i];
Uses.insert(Reg); Uses.insert(Reg);
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
Uses.insert(*Subreg); Uses.insert(*Subreg);
} }
@ -84,7 +84,7 @@ static void TrackDefUses(MachineInstr *MI,
for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) { for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
unsigned Reg = LocalDefs[i]; unsigned Reg = LocalDefs[i];
Defs.insert(Reg); Defs.insert(Reg);
for (const unsigned *Subreg = TRI->getSubRegisters(Reg); for (const uint16_t *Subreg = TRI->getSubRegisters(Reg);
*Subreg; ++Subreg) *Subreg; ++Subreg)
Defs.insert(*Subreg); Defs.insert(*Subreg);
if (Reg == ARM::CPSR) if (Reg == ARM::CPSR)

8
lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -235,7 +235,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters(
// //
// Check if we can use a double-word store. // Check if we can use a double-word store.
// //
const unsigned* SuperReg = TRI->getSuperRegisters(Reg); const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
// Assume that there is exactly one superreg. // Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
@ -243,7 +243,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters(
const TargetRegisterClass* SuperRegClass = 0; const TargetRegisterClass* SuperRegClass = 0;
if (ContiguousRegs && (i < CSI.size()-1)) { if (ContiguousRegs && (i < CSI.size()-1)) {
const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
assert(SuperRegNext[0] && !SuperRegNext[1] && assert(SuperRegNext[0] && !SuperRegNext[1] &&
"Expected exactly one superreg"); "Expected exactly one superreg");
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
@ -295,14 +295,14 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters(
// //
// Check if we can use a double-word load. // Check if we can use a double-word load.
// //
const unsigned* SuperReg = TRI->getSuperRegisters(Reg); const uint16_t* SuperReg = TRI->getSuperRegisters(Reg);
const TargetRegisterClass* SuperRegClass = 0; const TargetRegisterClass* SuperRegClass = 0;
// Assume that there is exactly one superreg. // Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
bool CanUseDblLoad = false; bool CanUseDblLoad = false;
if (ContiguousRegs && (i < CSI.size()-1)) { if (ContiguousRegs && (i < CSI.size()-1)) {
const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg());
assert(SuperRegNext[0] && !SuperRegNext[1] && assert(SuperRegNext[0] && !SuperRegNext[1] &&
"Expected exactly one superreg"); "Expected exactly one superreg");
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);

4
lib/Target/Mips/MipsExpandPseudo.cpp
View File

@ -95,7 +95,7 @@ void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc(); DebugLoc dl = I->getDebugLoc();
const unsigned* SubReg = const uint16_t* SubReg =
TM.getRegisterInfo()->getSubRegisters(DstReg); TM.getRegisterInfo()->getSubRegisters(DstReg);
// mtc1 Lo, $fp // mtc1 Lo, $fp
@ -111,7 +111,7 @@ void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB,
unsigned N = I->getOperand(2).getImm(); unsigned N = I->getOperand(2).getImm();
const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
DebugLoc dl = I->getDebugLoc(); DebugLoc dl = I->getDebugLoc();
const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N)); BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
} }

2
lib/Target/Mips/MipsFrameLowering.cpp
View File

@ -216,7 +216,7 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
// If Reg is a double precision register, emit two cfa_offsets, // If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers. // one for each of the paired single precision registers.
if (Mips::AFGR64RegisterClass->contains(Reg)) { if (Mips::AFGR64RegisterClass->contains(Reg)) {
const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg);
MachineLocation DstML0(MachineLocation::VirtualFP, Offset); MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
MachineLocation SrcML0(*SubRegs); MachineLocation SrcML0(*SubRegs);

14
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -288,7 +288,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
} }
OS << "};\n\n"; OS << "};\n\n";
OS << "extern const unsigned " << TargetName << "SubRegsSet[] = {\n"; OS << "extern const uint16_t " << TargetName << "SubRegsSet[] = {\n";
// Emit the empty sub-registers list // Emit the empty sub-registers list
OS << " /* Empty_SubRegsSet */ 0,\n"; OS << " /* Empty_SubRegsSet */ 0,\n";
// Loop over all of the registers which have sub-registers, emitting the // Loop over all of the registers which have sub-registers, emitting the
@ -307,7 +307,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
} }
OS << "};\n\n"; OS << "};\n\n";
OS << "extern const unsigned " << TargetName << "SuperRegsSet[] = {\n"; OS << "extern const uint16_t " << TargetName << "SuperRegsSet[] = {\n";
// Emit the empty super-registers list // Emit the empty super-registers list
OS << " /* Empty_SuperRegsSet */ 0,\n"; OS << " /* Empty_SuperRegsSet */ 0,\n";
// Loop over all of the registers which have super-registers, emitting the // Loop over all of the registers which have super-registers, emitting the
@ -629,7 +629,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.getName(); std::string Name = RC.getName();
OS << "static const unsigned " << Name << "SubclassMask[] = {\n "; OS << "static const uint32_t " << Name << "SubclassMask[] = {\n ";
printBitVectorAsHex(OS, RC.getSubClasses(), 32); printBitVectorAsHex(OS, RC.getSubClasses(), 32);
OS << "\n};\n\n"; OS << "\n};\n\n";
} }
@ -863,8 +863,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " };\n assert(A && B && \"Missing regclass\");\n" OS << " };\n assert(A && B && \"Missing regclass\");\n"
<< " --Idx;\n" << " --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " const unsigned *TV = Table[B->getID()][Idx];\n" << " const uint32_t *TV = Table[B->getID()][Idx];\n"
<< " const unsigned *SC = A->getSubClassMask();\n" << " const uint32_t *SC = A->getSubClassMask();\n"
<< " for (unsigned i = 0; i != " << BVWords << "; ++i)\n" << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
<< " if (unsigned Common = TV[i] & SC[i])\n" << " if (unsigned Common = TV[i] & SC[i])\n"
<< " return getRegClass(32*i + CountTrailingZeros_32(Common));\n" << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
@ -875,8 +875,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the constructor of the class... // Emit the constructor of the class...
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << "extern const uint16_t " << TargetName << "RegOverlaps[];\n"; OS << "extern const uint16_t " << TargetName << "RegOverlaps[];\n";
OS << "extern const unsigned " << TargetName << "SubRegsSet[];\n"; OS << "extern const uint16_t " << TargetName << "SubRegsSet[];\n";
OS << "extern const unsigned " << TargetName << "SuperRegsSet[];\n"; OS << "extern const uint16_t " << TargetName << "SuperRegsSet[];\n";
if (SubRegIndices.size() != 0) if (SubRegIndices.size() != 0)
OS << "extern const uint16_t *get" << TargetName OS << "extern const uint16_t *get" << TargetName
<< "SubRegTable();\n"; << "SubRegTable();\n";