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https://github.com/c64scene-ar/llvm-6502.git
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It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
a4006c6dbf
commit
9eda68988e
@ -1021,7 +1021,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
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CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
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Callee = DAG.getLoad(getPointerTy(), dl,
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DAG.getEntryNode(), CPAddr, NULL, 0);
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DAG.getEntryNode(), CPAddr,
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PseudoSourceValue::getConstantPool(), 0);
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SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
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Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
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getPointerTy(), Callee, PICLabel);
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@ -1040,7 +1041,8 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
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CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
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Callee = DAG.getLoad(getPointerTy(), dl,
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DAG.getEntryNode(), CPAddr, NULL, 0);
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DAG.getEntryNode(), CPAddr,
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PseudoSourceValue::getConstantPool(), 0);
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SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
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Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
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getPointerTy(), Callee, PICLabel);
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@ -1224,7 +1226,8 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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ARMCP::CPValue, PCAdj, "tlsgd", true);
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SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
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Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
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Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
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Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
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PseudoSourceValue::getConstantPool(), 0);
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SDValue Chain = Argument.getValue(1);
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SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
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@ -1266,19 +1269,22 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
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ARMCP::CPValue, PCAdj, "gottpoff", true);
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Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
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Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
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PseudoSourceValue::getConstantPool(), 0);
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Chain = Offset.getValue(1);
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SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
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Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
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PseudoSourceValue::getConstantPool(), 0);
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} else {
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// local exec model
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
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Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
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Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
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Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
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PseudoSourceValue::getConstantPool(), 0);
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}
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// The address of the thread local variable is the add of the thread
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@ -1347,7 +1353,8 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
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}
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CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
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SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
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SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
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PseudoSourceValue::getConstantPool(), 0);
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SDValue Chain = Result.getValue(1);
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if (RelocM == Reloc::PIC_) {
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@ -1356,7 +1363,8 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
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}
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if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
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Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
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Result = DAG.getLoad(PtrVT, dl, Chain, Result,
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PseudoSourceValue::getGOT(), 0);
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return Result;
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}
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@ -1403,7 +1411,8 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
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CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
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SDValue Result =
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DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
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DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
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PseudoSourceValue::getConstantPool(), 0);
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SDValue Chain = Result.getValue(1);
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if (RelocM == Reloc::PIC_) {
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@ -1500,7 +1509,8 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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// Create load node to retrieve arguments from the stack.
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SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
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ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
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PseudoSourceValue::getFixedStack(FI), 0);
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} else {
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Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
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ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
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@ -1613,7 +1623,8 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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// Create load nodes to retrieve arguments from the stack.
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SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
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InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
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InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
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PseudoSourceValue::getFixedStack(FI), 0));
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}
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}
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@ -1649,7 +1660,8 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
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PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0);
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MemOps.push_back(Store);
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FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
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DAG.getConstant(4, getPointerTy()));
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@ -1849,12 +1861,14 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
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Addr, Op.getOperand(2), JTI, UId);
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}
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
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Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
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PseudoSourceValue::getJumpTable(), 0);
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Chain = Addr.getValue(1);
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Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
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return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
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} else {
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Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
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Addr = DAG.getLoad(PTy, dl, Chain, Addr,
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PseudoSourceValue::getJumpTable(), 0);
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Chain = Addr.getValue(1);
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return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
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}
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@ -362,7 +362,9 @@ multiclass T2I_ld<string opc, PatFrag opnode> {
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[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
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def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
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[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> {
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let isReMaterializable = 1;
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}
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}
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/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
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34
test/CodeGen/Thumb2/machine-licm.ll
Normal file
34
test/CodeGen/Thumb2/machine-licm.ll
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@ -0,0 +1,34 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
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; rdar://7353541
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; The generated code is no where near ideal. It's not recognizing the two
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; constantpool entries being loaded can be merged into one.
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@GV = external global i32 ; <i32*> [#uses=2]
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define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
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entry:
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%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb.nph
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bb.nph: ; preds = %entry
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; CHECK: BB#1
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; CHECK: ldr r{{[0-9]+}}, LCPI1_0
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; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1
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%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
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%i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
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%scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
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store i32 %3, i32* @GV, align 4
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%4 = add i32 %i.03, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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