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Add constant extender support to ALU32 instructions for V2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169284 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
a790bc12c1
commit
9ee1ec6115
@ -41,40 +41,54 @@ multiclass CMP32_rr<string OpcStr, PatFrag OpNode> {
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(OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
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}
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multiclass CMP32_rr_ri_s10<string OpcStr, PatFrag OpNode> {
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def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Imm:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), s10ImmPred:$c))]>;
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multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
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let CextOpcode = CextOp in {
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let InputType = "reg" in
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def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
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opExtentBits = 10, InputType = "imm" in
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
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}
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}
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multiclass CMP32_rr_ri_u9<string OpcStr, PatFrag OpNode> {
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def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Imm:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), u9ImmPred:$c))]>;
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multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
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let CextOpcode = CextOp in {
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let InputType = "reg" in
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def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
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opExtentBits = 9, InputType = "imm" in
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst),
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(OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
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}
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}
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multiclass CMP32_ri_u8<string OpcStr, PatFrag OpNode> {
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Imm:$c),
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u8Ext:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
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u8ImmPred:$c))]>;
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u8ExtPred:$c))]>;
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}
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multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Imm:$c),
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
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def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
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[(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
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s8ImmPred:$c))]>;
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s8ExtPred:$c))]>;
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}
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}
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@ -132,7 +146,7 @@ defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
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multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
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(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
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") $dst = ")#mnemonic#"($src2, #$src3)",
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[]>;
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@ -146,17 +160,19 @@ multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
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}
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}
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let InputType = "imm" in
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let isExtendable = 1, InputType = "imm" in
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multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
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let isPredicable = 1 in
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
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isPredicable = 1 in
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def #NAME# : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s16Imm:$src2),
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(ins IntRegs:$src1, s16Ext:$src2),
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"$dst = "#mnemonic#"($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
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(s16ImmPred:$src2)))]>;
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(s16ExtPred:$src2)))]>;
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let neverHasSideEffects = 1, isPredicated = 1 in {
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let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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neverHasSideEffects = 1, isPredicated = 1 in {
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defm Pt : ALU32ri_Pred<mnemonic, 0>;
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defm NotPt : ALU32ri_Pred<mnemonic, 1>;
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}
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@ -165,23 +181,26 @@ multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
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defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
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CextOpcode = "OR", InputType = "imm" in
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def OR_ri : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s10Imm:$src2),
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(ins IntRegs:$src1, s10Ext:$src2),
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"$dst = or($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
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s10ImmPred:$src2))]>;
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s10ExtPred:$src2))]>, ImmRegRel;
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def NOT_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1),
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"$dst = not($src1)",
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[(set (i32 IntRegs:$dst), (not (i32 IntRegs:$src1)))]>;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
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InputType = "imm", CextOpcode = "AND" in
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def AND_ri : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s10Imm:$src2),
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(ins IntRegs:$src1, s10Ext:$src2),
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"$dst = and($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
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s10ImmPred:$src2))]>;
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s10ExtPred:$src2))]>, ImmRegRel;
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// Negate.
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def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = neg($src1)",
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@ -193,10 +212,13 @@ def NOP : ALU32_rr<(outs), (ins),
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[]>;
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// Rd32=sub(#s10,Rs32)
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
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CextOpcode = "SUB", InputType = "imm" in
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def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
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(ins s10Imm:$src1, IntRegs:$src2),
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(ins s10Ext:$src1, IntRegs:$src2),
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"$dst = sub(#$src1, $src2)",
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[(set IntRegs:$dst, (sub s10ImmPred:$src1, IntRegs:$src2))]>;
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[(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
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ImmRegRel;
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multiclass TFR_Pred<bit PredNot> {
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@ -331,32 +353,38 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
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"$dst = vmux($src1, $src2, $src3)",
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[]>;
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let CextOpcode = "MUX", InputType = "reg" in
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def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
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IntRegs:$src2, IntRegs:$src3),
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"$dst = mux($src1, $src2, $src3)",
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[(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
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(i32 IntRegs:$src2),
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(i32 IntRegs:$src3))))]>;
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
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(i32 IntRegs:$src3))))]>, ImmRegRel;
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def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
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CextOpcode = "MUX", InputType = "imm" in
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def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
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IntRegs:$src3),
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"$dst = mux($src1, #$src2, $src3)",
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[(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
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s8ImmPred:$src2,
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(i32 IntRegs:$src3))))]>;
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
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(i32 IntRegs:$src3))))]>, ImmRegRel;
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let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
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CextOpcode = "MUX", InputType = "imm" in
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def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
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s8Imm:$src3),
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s8Ext:$src3),
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"$dst = mux($src1, $src2, #$src3)",
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[(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
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(i32 IntRegs:$src2),
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s8ImmPred:$src3)))]>;
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[(set (i32 IntRegs:$dst),
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(i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
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s8ExtPred:$src3)))]>, ImmRegRel;
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def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Imm:$src2,
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
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def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
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s8Imm:$src3),
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"$dst = mux($src1, #$src2, #$src3)",
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[(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
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s8ImmPred:$src2,
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s8ExtPred:$src2,
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s8ImmPred:$src3)))]>;
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// Shift halfword.
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@ -427,11 +455,11 @@ def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
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[]>;
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// Compare.
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defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", setugt>;
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defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", setgt>;
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defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
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defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
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defm CMPLT : CMP32_rr<"cmp.lt", setlt>;
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defm CMPLTU : CMP32_rr<"cmp.ltu", setult>;
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defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", seteq>;
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defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
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defm CMPGE : CMP32_ri_s8<"cmp.ge", setge>;
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defm CMPGEU : CMP32_ri_u8<"cmp.geu", setuge>;
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//===----------------------------------------------------------------------===//
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