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Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
forget to right shift the source by 32 first. rdar://9287902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2952,7 +2952,10 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
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DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
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DAG.getConstant(32, MVT::i32));
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}
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} else if (VT == MVT::f32)
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Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
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DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
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DAG.getConstant(32, MVT::i32));
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Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
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Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
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@ -44,15 +44,32 @@ entry:
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define i32 @test4() ssp {
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entry:
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; SOFT: test4:
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; SOFT: vcvt.f32.f64 s0,
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; SOFT: vmov.i32 [[REG4:(d[0-9]+)]], #0x80000000
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; SOFT: vbic [[REG5:(d[0-9]+)]], d0, [[REG4]]
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; SOFT: vorr d0, [[REG4]], [[REG5]]
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; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
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; SOFT: vcvt.f32.f64 s0, [[REG4]]
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; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
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; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
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; SOFT: vbsl [[REG5]], [[REG4]], d0
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%call80 = tail call double @copysign(double 1.000000e+00, double undef)
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%conv81 = fptrunc double %call80 to float
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%tmp88 = bitcast float %conv81 to i32
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ret i32 %tmp88
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}
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; rdar://9287902
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define float @test5() nounwind {
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entry:
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; SOFT: test5:
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; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
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; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
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; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
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; SOFT: vbsl [[REG6]], [[REG7]],
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%0 = tail call double (...)* @bar() nounwind
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%1 = fptrunc double %0 to float
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%2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
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%3 = fadd float %1, %2
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ret float %3
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}
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declare double @bar(...)
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declare double @copysign(double, double) nounwind
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declare float @copysignf(float, float) nounwind
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