From 9efce638d307b2c71bd7f0258d47501661434c27 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 26 Sep 2007 06:25:56 +0000 Subject: [PATCH] Allow copyRegToReg to emit cross register classes copies. Tested with "make check"! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 3 +- lib/CodeGen/LowerSubregs.cpp | 8 ++--- lib/CodeGen/PHIElimination.cpp | 4 +-- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 10 +++--- .../SelectionDAG/ScheduleDAGSimple.cpp | 6 ++-- lib/CodeGen/TwoAddressInstructionPass.cpp | 2 +- lib/CodeGen/VirtRegMap.cpp | 7 ++-- lib/Target/ARM/ARMRegisterInfo.cpp | 14 +++++--- lib/Target/ARM/ARMRegisterInfo.h | 3 +- lib/Target/Alpha/AlphaRegisterInfo.cpp | 14 +++++--- lib/Target/Alpha/AlphaRegisterInfo.h | 3 +- lib/Target/IA64/IA64RegisterInfo.cpp | 9 +++-- lib/Target/IA64/IA64RegisterInfo.h | 3 +- lib/Target/Mips/MipsRegisterInfo.cpp | 10 ++++-- lib/Target/Mips/MipsRegisterInfo.h | 3 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 20 +++++++---- lib/Target/PowerPC/PPCRegisterInfo.h | 3 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 14 +++++--- lib/Target/Sparc/SparcRegisterInfo.h | 3 +- lib/Target/X86/X86RegisterInfo.cpp | 34 +++++++++++-------- lib/Target/X86/X86RegisterInfo.h | 3 +- 21 files changed, 115 insertions(+), 61 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index dab5d20b3c2..14ed6948e97 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -506,7 +506,8 @@ public: virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const = 0; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const = 0; /// reMaterialize - Re-issue the specified 'original' instruction at the /// specific location targeting a new destination register. diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 7acd03e1ccb..ba2a193ca40 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -88,7 +88,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC); + MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); MachineBasicBlock::iterator dMI = MI; DOUT << "subreg: " << *(--dMI); } @@ -157,7 +157,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getSSARegMap()->getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1); + MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -184,7 +184,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0); + MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -206,7 +206,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getSSARegMap()->getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1); + MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index fec9e2ec327..ffec6ca6d78 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -135,7 +135,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, // into the phi node destination. // const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC); + RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); // Update live variable information if there is any... LiveVariables *LV = getAnalysisToUpdate(); @@ -200,7 +200,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = opBlock.getFirstTerminator(); // Insert the copy. - RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC); + RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); // Now update live variable information if we have it. Otherwise we're done if (!LV) continue; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index b77512228cf..a6e32b2bfad 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -365,7 +365,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, } else { // Create the reg, emit the copy. VRBase = RegMap->createVirtualRegister(TRC); - MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC); + MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } if (InstanceNo > 0) @@ -769,7 +769,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, TRC = getPhysicalRegisterRegClass(MRI, Node->getOperand(2).getValueType(), InReg); - MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC); + MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } break; } @@ -854,9 +854,11 @@ void ScheduleDAG::EmitSchedule() { if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) { for (MachineFunction::livein_iterator LI = MF.livein_begin(), E = MF.livein_end(); LI != E; ++LI) - if (LI->second) + if (LI->second) { + const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, - LI->first, RegMap->getRegClass(LI->second)); + LI->first, RC, RC); + } } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp index 286ef1fa668..4f0a74bfee6 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp @@ -684,9 +684,11 @@ void ScheduleDAGSimple::EmitAll() { if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) { for (MachineFunction::livein_iterator LI = MF.livein_begin(), E = MF.livein_end(); LI != E; ++LI) - if (LI->second) + if (LI->second) { + const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, - LI->first, RegMap->getRegClass(LI->second)); + LI->first, RC, RC); + } } DenseMap VRBaseMap; diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 372b1b3db24..9c32388e790 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -192,7 +192,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { InstructionRearranged: const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); - MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); + MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); MachineBasicBlock::iterator prevMi = prior(mi); DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 8a1432ec897..c6ac4b208d0 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -926,7 +926,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg); MF.setPhysRegUsed(DesignatedReg); ReusedOperands.markClobbered(DesignatedReg); - MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC); + MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); MachineInstr *CopyMI = prior(MII); UpdateKills(*CopyMI, RegKills, KillOps); @@ -1009,8 +1009,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { DOUT << "Promoted Load To Copy: " << MI; if (DestReg != InReg) { - MRI->copyRegToReg(MBB, &MI, DestReg, InReg, - MF.getSSARegMap()->getRegClass(VirtReg)); + const TargetRegisterClass *RC = + MF.getSSARegMap()->getRegClass(VirtReg); + MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); // Revisit the copy so we make sure to notice the effects of the // operation on the destreg (either needing to RA it if it's // virtual or needing to clobber any values if it's physical). diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index eda31b0ca9d..e6d99e590c6 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -183,8 +183,14 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - if (RC == ARM::GPRRegisterClass) { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) @@ -192,10 +198,10 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, else BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0); - } else if (RC == ARM::SPRRegisterClass) + } else if (DestRC == ARM::SPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0); - else if (RC == ARM::DPRRegisterClass) + else if (DestRC == ARM::DPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg) .addImm((int64_t)ARMCC::AL).addReg(0); else diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 614eaec5b7c..7a2fd2c6cbc 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -58,7 +58,8 @@ public: void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 59d3e817d9b..08c4c94c031 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -141,13 +141,19 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (RC == Alpha::GPRCRegisterClass) { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Alpha::GPRCRegisterClass) { BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F4RCRegisterClass) { + } else if (DestRC == Alpha::F4RCRegisterClass) { BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F8RCRegisterClass) { + } else if (DestRC == Alpha::F8RCRegisterClass) { BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); } else { cerr << "Attempt to copy register that is not GPR or FPR"; diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index 354c3a12f3a..573d6eb54da 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -48,7 +48,8 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 08327f2efb2..15a0d4ab947 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -83,9 +83,14 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } - if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg) .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index 162ad5ae425..52e8ed354fc 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -42,7 +42,8 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index a946e46fa54..68ad38aed49 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -109,9 +109,15 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void MipsRegisterInfo:: copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { - if (RC == Mips::CPURegsRegisterClass) + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Mips::CPURegsRegisterClass) BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO) .addReg(SrcReg); else diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 2727910972d..b992e2e16d6 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -55,7 +55,8 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 2f1990e0170..158111b2847 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -226,18 +226,24 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - if (RC == PPC::GPRCRegisterClass) { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == PPC::GPRCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == PPC::G8RCRegisterClass) { + } else if (DestRC == PPC::G8RCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == PPC::F4RCRegisterClass) { + } else if (DestRC == PPC::F4RCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); - } else if (RC == PPC::F8RCRegisterClass) { + } else if (DestRC == PPC::F8RCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); - } else if (RC == PPC::CRRCRegisterClass) { + } else if (DestRC == PPC::CRRCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); - } else if (RC == PPC::VRRCRegisterClass) { + } else if (DestRC == PPC::VRRCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { cerr << "Attempt to copy register that is not GPR or FPR"; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 19bec1ca7f8..097d60cc9d2 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -47,7 +47,8 @@ public: void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 1981b4fe30b..d3ea07b1215 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -65,12 +65,18 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - if (RC == SP::IntRegsRegisterClass) + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == SP::IntRegsRegisterClass) BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); - else if (RC == SP::FPRegsRegisterClass) + else if (DestRC == SP::FPRegsRegisterClass) BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg); - else if (RC == SP::DFPRegsRegisterClass) + else if (DestRC == SP::DFPRegsRegisterClass) BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) .addReg(SrcReg); else diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index bcb09d475e1..a0e6fc239d5 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -42,7 +42,8 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1fdee671ef9..98955a305ed 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -231,33 +231,39 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + unsigned Opc; - if (RC == &X86::GR64RegClass) { + if (DestRC == &X86::GR64RegClass) { Opc = X86::MOV64rr; - } else if (RC == &X86::GR32RegClass) { + } else if (DestRC == &X86::GR32RegClass) { Opc = X86::MOV32rr; - } else if (RC == &X86::GR16RegClass) { + } else if (DestRC == &X86::GR16RegClass) { Opc = X86::MOV16rr; - } else if (RC == &X86::GR8RegClass) { + } else if (DestRC == &X86::GR8RegClass) { Opc = X86::MOV8rr; - } else if (RC == &X86::GR32_RegClass) { + } else if (DestRC == &X86::GR32_RegClass) { Opc = X86::MOV32_rr; - } else if (RC == &X86::GR16_RegClass) { + } else if (DestRC == &X86::GR16_RegClass) { Opc = X86::MOV16_rr; - } else if (RC == &X86::RFP32RegClass) { + } else if (DestRC == &X86::RFP32RegClass) { Opc = X86::MOV_Fp3232; - } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { + } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { Opc = X86::MOV_Fp6464; - } else if (RC == &X86::RFP80RegClass) { + } else if (DestRC == &X86::RFP80RegClass) { Opc = X86::MOV_Fp8080; - } else if (RC == &X86::FR32RegClass) { + } else if (DestRC == &X86::FR32RegClass) { Opc = X86::FsMOVAPSrr; - } else if (RC == &X86::FR64RegClass) { + } else if (DestRC == &X86::FR64RegClass) { Opc = X86::FsMOVAPDrr; - } else if (RC == &X86::VR128RegClass) { + } else if (DestRC == &X86::VR128RegClass) { Opc = X86::MOVAPSrr; - } else if (RC == &X86::VR64RegClass) { + } else if (DestRC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64rr; } else { assert(0 && "Unknown regclass"); diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 462bcc3c6e2..e0d1c6a4bf3 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -78,7 +78,8 @@ public: void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const;