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Generate branch machine instructions with MachineBasicBlock operands instead of
LLVM BasicBlock operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13566 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1379,7 +1379,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
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if (!BI.isConditional()) { // Unconditional branch?
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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return;
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}
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@ -1392,12 +1392,12 @@ void ISel::visitBranchInst(BranchInst &BI) {
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BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
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if (BI.getSuccessor(1) == NextBB) {
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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} else {
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BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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}
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return;
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}
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@ -1429,14 +1429,16 @@ void ISel::visitBranchInst(BranchInst &BI) {
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};
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if (BI.getSuccessor(0) != NextBB) {
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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if (BI.getSuccessor(1) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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} else {
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// Change to the inverse condition...
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if (BI.getSuccessor(1) != NextBB) {
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OpNum ^= 1;
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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}
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}
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}
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@ -1379,7 +1379,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
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if (!BI.isConditional()) { // Unconditional branch?
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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return;
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}
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@ -1392,12 +1392,12 @@ void ISel::visitBranchInst(BranchInst &BI) {
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BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
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if (BI.getSuccessor(1) == NextBB) {
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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} else {
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BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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if (BI.getSuccessor(0) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
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}
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return;
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}
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@ -1429,14 +1429,16 @@ void ISel::visitBranchInst(BranchInst &BI) {
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};
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if (BI.getSuccessor(0) != NextBB) {
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
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.addMBB(MBBMap[BI.getSuccessor(0)]);
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if (BI.getSuccessor(1) != NextBB)
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
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} else {
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// Change to the inverse condition...
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if (BI.getSuccessor(1) != NextBB) {
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OpNum ^= 1;
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
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BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
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.addMBB(MBBMap[BI.getSuccessor(1)]);
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}
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}
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}
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