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Fix vector sign extend to put the source and destination types in the

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correct places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Greene 2011-01-31 20:39:01 +00:00
parent fd2ad8783c
commit 9f08f60993
1 changed files with 3 additions and 3 deletions
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6
lib/Target/CellSPU/SPUInstrInfo.td
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@ -1167,10 +1167,10 @@ class XSHWRegInst<RegisterClass rclass>:
[(set rclass:$rDest, (sext R16C:$rSrc))]>;
multiclass ExtendHalfwordWord {
def v4i32: XSHWVecInst<v4i32, v8i16>;
def v4i32: XSHWVecInst<v8i16, v4i32>;
def r16: XSHWRegInst<R32C>;
def r32: XSHWInRegInst<R32C,
[(set R32C:$rDest, (sext_inreg R32C:$rSrc, i16))]>;
def r64: XSHWInRegInst<R64C, [/* no pattern */]>;