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Update note, with the SROA change, we now produce:

Browse Source 
_pairtest:
        movl 8(%esp), %eax
        movl 4(%esp), %ecx
        movd %eax, %xmm0
        movd %ecx, %xmm1
        addss %xmm0, %xmm1
        movl 12(%esp), %eax
        movss %xmm1, (%eax)
        ret

instead of:

_pairtest:
        subl $12, %esp
        movl 20(%esp), %eax
        movl %eax, 4(%esp)
        movl 16(%esp), %eax
        movl %eax, (%esp)
        movss (%esp), %xmm0
        addss 4(%esp), %xmm0
        movl 24(%esp), %eax
        movss %xmm0, (%eax)
        addl $12, %esp
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32427 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-12-11 01:20:25 +00:00
parent 509f85140c
commit 9f09fa2900
1 changed files with 11 additions and 10 deletions
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21
lib/Target/X86/README.txt
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@ -430,16 +430,13 @@ void pairtest(pair P, float *FP) {
We currently generate this code with llvmgcc4:
_pairtest:
subl $12, %esp
movl 20(%esp), %eax
movl %eax, 4(%esp)
movl 16(%esp), %eax
movl %eax, (%esp)
movss (%esp), %xmm0
addss 4(%esp), %xmm0
movl 24(%esp), %eax
movss %xmm0, (%eax)
addl $12, %esp
movl 8(%esp), %eax
movl 4(%esp), %ecx
movd %eax, %xmm0
movd %ecx, %xmm1
addss %xmm0, %xmm1
movl 12(%esp), %eax
movss %xmm1, (%eax)
ret
we should be able to generate:
@ -455,6 +452,10 @@ integer chunks. It does this so that structs like {short,short} are passed in
a single 32-bit integer stack slot. We should handle the safe cases above much
nicer, while still handling the hard cases.
While true in general, in this specific case we could do better by promoting
load int + bitcast to float -> load fload. This basically needs alignment info,
the code is already implemented (but disabled) in dag combine).
//===---------------------------------------------------------------------===//
Another instruction selector deficiency: