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Model calls as *both* using *and* killing O0..O5, because callees use the

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argument values passed in (so they're not dead until *after* the call),
and callees are free to modify those registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-10-10 19:57:20 +00:00
parent 50094edf96
commit 9f0cecd438
2 changed files with 4 additions and 2 deletions
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3
lib/Target/Sparc/SparcInstrInfo.td
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@ -193,7 +193,8 @@ def FBO : FPBranchV8<0b1111, "fbo">;
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
let Uses = [O0, O1, O2, O3, O4, O5], Defs = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1 in {
// pc-relative call:
def CALL : InstV8 {
bits<30> disp;

3
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -193,7 +193,8 @@ def FBO : FPBranchV8<0b1111, "fbo">;
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Defs = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
let Uses = [O0, O1, O2, O3, O4, O5], Defs = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1 in {
// pc-relative call:
def CALL : InstV8 {
bits<30> disp;