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[SystemZ] Define the return instruction as a pseudo alias of BR

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This is the first of a few patches to reduce the dupliation of encoding
information.  The return instruction is a normal BR in which one of the
registers is fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191364 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-09-25 10:20:08 +00:00
parent c2b840cb7c
commit 9f3f4bf377
3 changed files with 23 additions and 8 deletions
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12
lib/Target/SystemZ/SystemZAsmPrinter.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/Mangler.h"
@ -26,9 +27,16 @@
using namespace llvm;
void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
SystemZMCInstLower Lower(Mang, MF->getContext(), *this);
MCInst LoweredMI;
Lower.lower(MI, LoweredMI);
switch (MI->getOpcode()) {
case SystemZ::Return:
LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
break;
default:
SystemZMCInstLower(Mang, MF->getContext(), *this).lower(MI, LoweredMI);
break;
}
OutStreamer.EmitInstruction(LoweredMI);
}

10
lib/Target/SystemZ/SystemZInstrFormats.td
View File

@ -1467,3 +1467,13 @@ multiclass StringRRE<string mnemonic, bits<16> opcode,
[(set GR64:$end, (operator GR64:$start1, GR64:$start2,
GR32:$char))]>;
}
// A pseudo instruction that is a direct alias of a real instruction.
// These aliases are used in cases where a particular register operand is
// fixed or where the same instruction is used with different register sizes.
// The size parameter is the size in bytes of the associated real instruction.
class Alias<int size, dag outs, dag ins, list<dag> pattern>
: InstSystemZ<size, outs, ins, "", pattern> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}

9
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -32,12 +32,9 @@ let neverHasSideEffects = 1 in {
// Control flow instructions
//===----------------------------------------------------------------------===//
// A return instruction. R1 is the condition-code mask (all 1s)
// and R2 is the target address, which is always stored in %r14.
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
}
// A return instruction (br %r14).
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
// Unconditional branches. R1 is the condition-code mask (all 1s).
let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {