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https://github.com/c64scene-ar/llvm-6502.git
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Flesh out GEP support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13421 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -477,12 +477,62 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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///
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void V8ISel::emitGEPOperation (MachineBasicBlock *BB,
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void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg) {
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std::cerr << "Sorry, GEPs not yet supported\n";
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abort ();
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const TargetData &TD = TM.getTargetData ();
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const Type *Ty = Src->getType ();
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unsigned basePtrReg = getReg (Src);
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// GEPs have zero or more indices; we must perform a struct access
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// or array access for each one.
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for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
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++oi) {
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Value *idx = *oi;
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unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
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if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
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// It's a struct access. idx is the index into the structure,
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// which names the field. Use the TargetData structure to
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// pick out what the layout of the structure is in memory.
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// Use the (constant) structure index's value to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
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// Emit an ADD to add memberOffset to the basePtr.
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BuildMI (*MBB, IP, V8::ADDri, 2,
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nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
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// The next type is the member of the structure selected by the
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// index.
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Ty = StTy->getElementType (fieldIndex);
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} else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
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// It's an array or pointer access: [ArraySize x ElementType].
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// We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
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// must find the size of the pointed-to type (Not coincidentally, the next
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// type is the type of the elements in the array).
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Ty = SqTy->getElementType ();
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unsigned elementSize = TD.getTypeSize (Ty);
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unsigned idxReg = getReg (idx, MBB, IP);
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unsigned OffsetReg = makeAnotherReg (Type::IntTy);
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unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
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BuildMI (*MBB, IP, V8::ORri, 2,
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elementSizeReg).addZImm (elementSize).addReg (V8::G0);
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// Emit a SMUL to multiply the register holding the index by
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// elementSize, putting the result in OffsetReg.
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BuildMI (*MBB, IP, V8::SMULrr, 2,
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OffsetReg).addReg (elementSizeReg).addReg (idxReg);
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// Emit an ADD to add OffsetReg to the basePtr.
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BuildMI (*MBB, IP, V8::ADDrr, 2,
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nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
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}
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basePtrReg = nextBasePtrReg;
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}
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// After we have processed all the indices, the result is left in
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// basePtrReg. Move it to the register where we were expected to
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// put the answer.
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BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
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}
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void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
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@ -477,12 +477,62 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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///
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void V8ISel::emitGEPOperation (MachineBasicBlock *BB,
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void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg) {
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std::cerr << "Sorry, GEPs not yet supported\n";
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abort ();
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const TargetData &TD = TM.getTargetData ();
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const Type *Ty = Src->getType ();
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unsigned basePtrReg = getReg (Src);
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// GEPs have zero or more indices; we must perform a struct access
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// or array access for each one.
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for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
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++oi) {
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Value *idx = *oi;
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unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
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if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
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// It's a struct access. idx is the index into the structure,
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// which names the field. Use the TargetData structure to
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// pick out what the layout of the structure is in memory.
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// Use the (constant) structure index's value to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
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// Emit an ADD to add memberOffset to the basePtr.
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BuildMI (*MBB, IP, V8::ADDri, 2,
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nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
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// The next type is the member of the structure selected by the
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// index.
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Ty = StTy->getElementType (fieldIndex);
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} else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
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// It's an array or pointer access: [ArraySize x ElementType].
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// We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
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// must find the size of the pointed-to type (Not coincidentally, the next
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// type is the type of the elements in the array).
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Ty = SqTy->getElementType ();
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unsigned elementSize = TD.getTypeSize (Ty);
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unsigned idxReg = getReg (idx, MBB, IP);
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unsigned OffsetReg = makeAnotherReg (Type::IntTy);
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unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
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BuildMI (*MBB, IP, V8::ORri, 2,
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elementSizeReg).addZImm (elementSize).addReg (V8::G0);
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// Emit a SMUL to multiply the register holding the index by
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// elementSize, putting the result in OffsetReg.
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BuildMI (*MBB, IP, V8::SMULrr, 2,
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OffsetReg).addReg (elementSizeReg).addReg (idxReg);
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// Emit an ADD to add OffsetReg to the basePtr.
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BuildMI (*MBB, IP, V8::ADDrr, 2,
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nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
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}
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basePtrReg = nextBasePtrReg;
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}
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// After we have processed all the indices, the result is left in
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// basePtrReg. Move it to the register where we were expected to
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// put the answer.
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BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
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}
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void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
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@ -477,12 +477,62 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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///
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void V8ISel::emitGEPOperation (MachineBasicBlock *BB,
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void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg) {
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std::cerr << "Sorry, GEPs not yet supported\n";
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abort ();
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const TargetData &TD = TM.getTargetData ();
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const Type *Ty = Src->getType ();
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unsigned basePtrReg = getReg (Src);
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// GEPs have zero or more indices; we must perform a struct access
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// or array access for each one.
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for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
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++oi) {
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Value *idx = *oi;
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unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
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if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
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// It's a struct access. idx is the index into the structure,
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// which names the field. Use the TargetData structure to
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// pick out what the layout of the structure is in memory.
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// Use the (constant) structure index's value to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
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// Emit an ADD to add memberOffset to the basePtr.
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BuildMI (*MBB, IP, V8::ADDri, 2,
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nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
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// The next type is the member of the structure selected by the
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// index.
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Ty = StTy->getElementType (fieldIndex);
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} else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
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// It's an array or pointer access: [ArraySize x ElementType].
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// We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
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// must find the size of the pointed-to type (Not coincidentally, the next
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// type is the type of the elements in the array).
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Ty = SqTy->getElementType ();
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unsigned elementSize = TD.getTypeSize (Ty);
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unsigned idxReg = getReg (idx, MBB, IP);
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unsigned OffsetReg = makeAnotherReg (Type::IntTy);
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unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
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BuildMI (*MBB, IP, V8::ORri, 2,
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elementSizeReg).addZImm (elementSize).addReg (V8::G0);
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// Emit a SMUL to multiply the register holding the index by
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// elementSize, putting the result in OffsetReg.
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BuildMI (*MBB, IP, V8::SMULrr, 2,
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OffsetReg).addReg (elementSizeReg).addReg (idxReg);
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// Emit an ADD to add OffsetReg to the basePtr.
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BuildMI (*MBB, IP, V8::ADDrr, 2,
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nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
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}
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basePtrReg = nextBasePtrReg;
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}
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// After we have processed all the indices, the result is left in
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// basePtrReg. Move it to the register where we were expected to
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// put the answer.
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BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
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}
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void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
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@ -477,12 +477,62 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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///
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void V8ISel::emitGEPOperation (MachineBasicBlock *BB,
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void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned TargetReg) {
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std::cerr << "Sorry, GEPs not yet supported\n";
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abort ();
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const TargetData &TD = TM.getTargetData ();
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const Type *Ty = Src->getType ();
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unsigned basePtrReg = getReg (Src);
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// GEPs have zero or more indices; we must perform a struct access
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// or array access for each one.
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for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
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++oi) {
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Value *idx = *oi;
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unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
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if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
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// It's a struct access. idx is the index into the structure,
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// which names the field. Use the TargetData structure to
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// pick out what the layout of the structure is in memory.
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// Use the (constant) structure index's value to find the
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// right byte offset from the StructLayout class's list of
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// structure member offsets.
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unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
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unsigned memberOffset =
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TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
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// Emit an ADD to add memberOffset to the basePtr.
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BuildMI (*MBB, IP, V8::ADDri, 2,
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nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
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// The next type is the member of the structure selected by the
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// index.
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Ty = StTy->getElementType (fieldIndex);
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} else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
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// It's an array or pointer access: [ArraySize x ElementType].
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// We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
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// must find the size of the pointed-to type (Not coincidentally, the next
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// type is the type of the elements in the array).
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Ty = SqTy->getElementType ();
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unsigned elementSize = TD.getTypeSize (Ty);
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unsigned idxReg = getReg (idx, MBB, IP);
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unsigned OffsetReg = makeAnotherReg (Type::IntTy);
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unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
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BuildMI (*MBB, IP, V8::ORri, 2,
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elementSizeReg).addZImm (elementSize).addReg (V8::G0);
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// Emit a SMUL to multiply the register holding the index by
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// elementSize, putting the result in OffsetReg.
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BuildMI (*MBB, IP, V8::SMULrr, 2,
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OffsetReg).addReg (elementSizeReg).addReg (idxReg);
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// Emit an ADD to add OffsetReg to the basePtr.
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BuildMI (*MBB, IP, V8::ADDrr, 2,
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nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
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}
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basePtrReg = nextBasePtrReg;
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}
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// After we have processed all the indices, the result is left in
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// basePtrReg. Move it to the register where we were expected to
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// put the answer.
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BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
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}
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void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
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