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Remove the TargetMachine forwards for TargetSubtargetInfo based

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information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-08-04 21:25:23 +00:00
parent ffa13eafbf
commit 9f85dccfc6
297 changed files with 2215 additions and 1721 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CodeGen/MachineInstr.cpp
+14 -6
View File
@@ -39,6 +39,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
@@ -265,7 +266,8 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
if (const MachineBasicBlock *MBB = MI->getParent())
if (const MachineFunction *MF = MBB->getParent())
TM = &MF->getTarget();
const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr;
const TargetRegisterInfo *TRI =
TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
switch (getType()) {
case MachineOperand::MO_Register:
@@ -1517,8 +1519,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
OS << " = ";
// Print the opcode name.
if (TM && TM->getInstrInfo())
OS << TM->getInstrInfo()->getName(getOpcode());
if (TM && TM->getSubtargetImpl()->getInstrInfo())
OS << TM->getSubtargetImpl()->getInstrInfo()->getName(getOpcode());
else
OS << "UNKNOWN";
@@ -1573,7 +1575,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (MRI.use_empty(Reg)) {
bool HasAliasLive = false;
for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
for (MCRegAliasIterator AI(
Reg, TM->getSubtargetImpl()->getRegisterInfo(), true);
AI.isValid(); ++AI) {
unsigned AliasReg = *AI;
if (!MRI.use_empty(AliasReg)) {
@@ -1606,7 +1609,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
else
MO.print(OS, TM);
} else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName(
MO.getImm());
} else if (i == AsmDescOp && MO.isImm()) {
// Pretty print the inline asm operand descriptor.
OS << '$' << AsmOpCount++;
@@ -1624,7 +1628,11 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
unsigned RCID = 0;
if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
if (TM)
OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
OS << ':'
<< TM->getSubtargetImpl()
->getRegisterInfo()
->getRegClass(RCID)
->getName();
else
OS << ":RC" << RCID;
}