6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Remove the TargetMachine forwards for TargetSubtargetInfo based

Browse Source 
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-08-04 21:25:23 +00:00
parent ffa13eafbf
commit 9f85dccfc6
297 changed files with 2215 additions and 1721 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/Sparc/SparcISelLowering.cpp
View File

@@ -915,7 +915,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
// Add a register mask operand representing the call-preserved registers.
const SparcRegisterInfo *TRI =
((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo();
const uint32_t *Mask = ((hasReturnsTwice)
? TRI->getRTCallPreservedMask(CallConv)
: TRI->getCallPreservedMask(CallConv));
@@ -1228,10 +1228,10 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
// Add a register mask operand representing the call-preserved registers.
const SparcRegisterInfo *TRI =
((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
const uint32_t *Mask = ((hasReturnsTwice)
? TRI->getRTCallPreservedMask(CLI.CallConv)
: TRI->getCallPreservedMask(CLI.CallConv));
getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo();
const uint32_t *Mask =
((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
: TRI->getCallPreservedMask(CLI.CallConv));
assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask));
@@ -1905,7 +1905,9 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
Ops.push_back(Symbol);
Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
const uint32_t *Mask = getTargetMachine()
.getRegisterInfo()->getCallPreservedMask(CallingConv::C);
.getSubtargetImpl()
->getRegisterInfo()
->getCallPreservedMask(CallingConv::C);
assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask));
Ops.push_back(InFlag);
@@ -2901,7 +2903,8 @@ MachineBasicBlock*
SparcTargetLowering::expandSelectCC(MachineInstr *MI,
MachineBasicBlock *BB,
unsigned BROpcode) const {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
const TargetInstrInfo &TII =
*getTargetMachine().getSubtargetImpl()->getInstrInfo();
DebugLoc dl = MI->getDebugLoc();
unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
@@ -2962,7 +2965,8 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
MachineBasicBlock *MBB,
unsigned Opcode,
unsigned CondCode) const {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
const TargetInstrInfo &TII =
*getTargetMachine().getSubtargetImpl()->getInstrInfo();
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
DebugLoc DL = MI->getDebugLoc();