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Set ARM if-conversion block size threshold to 10 instructions for now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-18 00:19:34 +00:00
parent 6ae3626a4f
commit 9f8cbd147c
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMISelLowering.cpp
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@ -124,6 +124,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
}
computeRegisterProperties();
// ARM does not have f32 extending load.
setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
@ -252,9 +253,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
setStackPointerRegisterToSaveRestore(ARM::SP);
setSchedulingPreference(SchedulingForRegPressure);
computeRegisterProperties();
setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
}