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[SystemZ] Use LOAD AND TEST for comparisons with -0
...since it os equivalent to comparison with +0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196580 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -46,9 +46,9 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
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defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
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defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
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defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
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}
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}
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def : CompareZeroFP<LTEBRCompare, FP32>;
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defm : CompareZeroFP<LTEBRCompare, FP32>;
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def : CompareZeroFP<LTDBRCompare, FP64>;
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defm : CompareZeroFP<LTDBRCompare, FP64>;
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def : CompareZeroFP<LTXBRCompare, FP128>;
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defm : CompareZeroFP<LTXBRCompare, FP128>;
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// Moves between 64-bit integer and floating-point registers.
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// Moves between 64-bit integer and floating-point registers.
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def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
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def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
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@@ -148,5 +148,8 @@ multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
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// Record that INSN is a LOAD AND TEST that can be used to compare
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// Record that INSN is a LOAD AND TEST that can be used to compare
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// registers in CLS against zero. The instruction has separate R1 and R2
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// registers in CLS against zero. The instruction has separate R1 and R2
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// operands, but they must be the same when the instruction is used like this.
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// operands, but they must be the same when the instruction is used like this.
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class CompareZeroFP<Instruction insn, RegisterOperand cls>
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multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> {
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: Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
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def : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
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// The sign of the zero makes no difference.
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def : Pat<(z_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>;
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}
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@@ -346,3 +346,22 @@ store:
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exit:
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exit:
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ret double %val
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ret double %val
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}
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}
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; Repeat f2 with a comparison against -0.
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define float @f17(float %a, float %b, float *%dest) {
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; CHECK-LABEL: f17:
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; CHECK: aebr %f0, %f2
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = fadd float %a, %b
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%cmp = fcmp olt float %res, -0.0
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br i1 %cmp, label %exit, label %store
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store:
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store float %b, float *%dest
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br label %exit
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exit:
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ret float %res
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}
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