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Add stub method for long shift codegen.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18100 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-11-22 08:02:06 +00:00
parent 6f0b77221c
commit 9ffcf9fddd
2 changed files with 42 additions and 0 deletions
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21
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -90,6 +90,9 @@ namespace {
MachineBasicBlock::iterator IP,
unsigned DestReg, const char *FuncName,
unsigned Op0Reg, unsigned Op1Reg);
void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
Instruction &I, unsigned DestReg, unsigned Op0Reg,
unsigned Op1Reg);
void visitBinaryOperator(Instruction &I);
void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
void visitSetCondInst(SetCondInst &I);
@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
}
void V8ISel::emitShift64 (MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP, Instruction &I,
unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) {
bool isSigned = I.getType()->isSigned();
switch (I.getOpcode ()) {
case Instruction::Shl:
case Instruction::Shr:
default:
std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
abort ();
}
}
void V8ISel::visitBinaryOperator (Instruction &I) {
unsigned DestReg = getReg (I);
unsigned Op0Reg = getReg (I.getOperand (0));
@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
return;
case Instruction::Shl:
case Instruction::Shr:
emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
return;
}
}

21
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -90,6 +90,9 @@ namespace {
MachineBasicBlock::iterator IP,
unsigned DestReg, const char *FuncName,
unsigned Op0Reg, unsigned Op1Reg);
void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
Instruction &I, unsigned DestReg, unsigned Op0Reg,
unsigned Op1Reg);
void visitBinaryOperator(Instruction &I);
void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
void visitSetCondInst(SetCondInst &I);
@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
}
void V8ISel::emitShift64 (MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP, Instruction &I,
unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) {
bool isSigned = I.getType()->isSigned();
switch (I.getOpcode ()) {
case Instruction::Shl:
case Instruction::Shr:
default:
std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
abort ();
}
}
void V8ISel::visitBinaryOperator (Instruction &I) {
unsigned DestReg = getReg (I);
unsigned Op0Reg = getReg (I.getOperand (0));
@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
return;
case Instruction::Shl:
case Instruction::Shr:
emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
return;
}
}