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Add stub method for long shift codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18100 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -90,6 +90,9 @@ namespace {
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MachineBasicBlock::iterator IP,
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unsigned DestReg, const char *FuncName,
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unsigned Op0Reg, unsigned Op1Reg);
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void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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Instruction &I, unsigned DestReg, unsigned Op0Reg,
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unsigned Op1Reg);
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void visitBinaryOperator(Instruction &I);
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void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
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void visitSetCondInst(SetCondInst &I);
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@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
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BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
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}
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void V8ISel::emitShift64 (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP, Instruction &I,
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unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) {
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bool isSigned = I.getType()->isSigned();
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switch (I.getOpcode ()) {
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case Instruction::Shl:
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case Instruction::Shr:
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default:
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std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
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abort ();
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}
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}
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void V8ISel::visitBinaryOperator (Instruction &I) {
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
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FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
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emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
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return;
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}
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}
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@ -90,6 +90,9 @@ namespace {
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MachineBasicBlock::iterator IP,
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unsigned DestReg, const char *FuncName,
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unsigned Op0Reg, unsigned Op1Reg);
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void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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Instruction &I, unsigned DestReg, unsigned Op0Reg,
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unsigned Op1Reg);
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void visitBinaryOperator(Instruction &I);
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void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
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void visitSetCondInst(SetCondInst &I);
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@ -1109,6 +1112,20 @@ void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
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BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
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}
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void V8ISel::emitShift64 (MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP, Instruction &I,
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unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg) {
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bool isSigned = I.getType()->isSigned();
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switch (I.getOpcode ()) {
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case Instruction::Shl:
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case Instruction::Shr:
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default:
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std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
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abort ();
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}
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}
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void V8ISel::visitBinaryOperator (Instruction &I) {
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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@ -1168,6 +1185,10 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
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FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
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emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
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return;
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}
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}
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