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[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -231,31 +231,48 @@ bool Filler::delayHasHazard(InstrIter candidate,
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return false;
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}
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// Helper function for getting a MachineOperand's register number and adding it
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// to RegDefs or RegUses.
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static void insertDefUse(const MachineOperand &MO,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses,
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unsigned ExcludedReg = 0) {
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
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return;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(InstrIter MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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// If MI is a call or return, just examine the explicit non-variadic operands.
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MCInstrDesc MCID = MI->getDesc();
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unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
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MI->getNumOperands();
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unsigned I, E = MI->getDesc().getNumOperands();
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// Add RA to RegDefs to prevent users of RA from going into delay slot.
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if (MI->isCall())
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for (I = 0; I != E; ++I)
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insertDefUse(MI->getOperand(I), RegDefs, RegUses);
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// If MI is a call, add RA to RegDefs to prevent users of RA from going into
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// delay slot.
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if (MI->isCall()) {
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RegDefs.insert(Mips::RA);
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for (unsigned i = 0; i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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return;
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}
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// Return if MI is a return.
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if (MI->isReturn())
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return;
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// Examine the implicit operands. Exclude register AT which is in the list of
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// clobbered registers of branch instructions.
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E = MI->getNumOperands();
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for (; I != E; ++I)
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insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
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}
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//returns true if the Reg or its alias is in the RegSet.
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