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enhance the immediate field encoding to know whether the immediate

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is pc relative or not, mark call and branches as pcrel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-02-12 22:27:07 +00:00
parent 3f7aa79c2a
commit a0331199fc
3 changed files with 59 additions and 23 deletions
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21
lib/Target/X86/X86InstrFormats.td
View File

@ -44,9 +44,11 @@ class ImmType<bits<3> val> {
}
def NoImm : ImmType<0>;
def Imm8 : ImmType<1>;
def Imm16 : ImmType<2>;
def Imm32 : ImmType<3>;
def Imm64 : ImmType<4>;
def Imm8PCRel : ImmType<2>;
def Imm16 : ImmType<3>;
def Imm32 : ImmType<4>;
def Imm32PCRel : ImmType<5>;
def Imm64 : ImmType<6>;
// FPFormat - This specifies what form this FP instruction has. This is used by
// the Floating-Point stackifier pass.
@ -126,6 +128,12 @@ class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
let Pattern = pattern;
let CodeSize = 3;
}
class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
let Pattern = pattern;
let CodeSize = 3;
}
class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm16, outs, ins, asm> {
@ -139,6 +147,13 @@ class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
let CodeSize = 3;
}
class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
let Pattern = pattern;
let CodeSize = 3;
}
// FPStack Instruction Templates:
// FPI - Floating Point Instruction template.
class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>

30
lib/Target/X86/X86InstrInfo.h
View File

@ -340,9 +340,11 @@ namespace X86II {
ImmShift = 13,
ImmMask = 7 << ImmShift,
Imm8 = 1 << ImmShift,
Imm16 = 2 << ImmShift,
Imm32 = 3 << ImmShift,
Imm64 = 4 << ImmShift,
Imm8PCRel = 2 << ImmShift,
Imm16 = 3 << ImmShift,
Imm32 = 4 << ImmShift,
Imm32PCRel = 5 << ImmShift,
Imm64 = 6 << ImmShift,
//===------------------------------------------------------------------===//
// FP Instruction Classification... Zero is non-fp instruction.
@ -408,12 +410,30 @@ namespace X86II {
static inline unsigned getSizeOfImm(unsigned TSFlags) {
switch (TSFlags & X86II::ImmMask) {
default: assert(0 && "Unknown immediate size");
case X86II::Imm8: return 1;
case X86II::Imm8:
case X86II::Imm8PCRel: return 1;
case X86II::Imm16: return 2;
case X86II::Imm32: return 4;
case X86II::Imm32:
case X86II::Imm32PCRel: return 4;
case X86II::Imm64: return 8;
}
}
/// isImmPCRel - Return true if the immediate of the specified instruction's
/// TSFlags indicates that it is pc relative.
static inline unsigned isImmPCRel(unsigned TSFlags) {
switch (TSFlags & X86II::ImmMask) {
default: assert(0 && "Unknown immediate size");
case X86II::Imm8PCRel:
case X86II::Imm32PCRel:
return true;
case X86II::Imm8:
case X86II::Imm16:
case X86II::Imm32:
case X86II::Imm64:
return false;
}
}
}
const int X86AddrNumOperands = 5;

13
lib/Target/X86/X86InstrInfo.td
View File

@ -616,17 +616,17 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
// Unconditional branches.
let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
def JMP_4 : Ii32<0xE9, RawFrm, (outs), (ins brtarget:$dst),
def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
"jmp\t$dst", [(br bb:$dst)]>;
def JMP_1 : Ii8 <0xEB, RawFrm, (outs), (ins brtarget8:$dst),
def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
"jmp\t$dst", []>;
}
// Conditional Branches.
let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
def _1 : Ii8 <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
def _4 : Ii32<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
[(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
}
}
@ -650,7 +650,8 @@ defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
// FIXME: What about the CX/RCX versions of this instruction?
let Uses = [ECX], isBranch = 1, isTerminator = 1 in
def JCXZ8 : Ii8<0xE3, RawFrm, (outs), (ins brtarget8:$dst), "jcxz\t$dst", []>;
def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
"jcxz\t$dst", []>;
// Indirect branches
@ -693,7 +694,7 @@ let isCall = 1 in
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
Uses = [ESP] in {
def CALLpcrel32 : Ii32<0xE8, RawFrm,
def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
(outs), (ins i32imm_pcrel:$dst,variable_ops),
"call\t$dst", []>;
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),