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https://github.com/c64scene-ar/llvm-6502.git
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ARMTargetParser: Normalising build attributes
Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu strings are using ARMTargetParser, it's time to make it a bit more conforming with what the ABI says. This commit adds some clarification on what build attributes are accepted and which are "non-standard". It also makes clear that the "defaultCPU" and "defaultArch" methods were really just build attribute getters. It also diverges from GCC's behaviour to say that armv2/armv3 are really an ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin
parent
fb421f446e
commit
a052a77187
@ -56,17 +56,19 @@ namespace ARM {
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AK_ARMV5,
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AK_ARMV5T,
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AK_ARMV5TE,
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AK_ARMV5TEJ,
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AK_ARMV6,
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AK_ARMV6J,
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AK_ARMV6K,
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AK_ARMV6T2,
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AK_ARMV6Z,
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AK_ARMV6ZK,
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AK_ARMV6M,
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AK_ARMV6SM,
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AK_ARMV7,
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AK_ARMV7A,
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AK_ARMV7R,
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AK_ARMV7M,
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AK_ARMV7EM,
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AK_ARMV8A,
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AK_ARMV8_1A,
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// Non-standard Arch names.
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@ -74,13 +76,11 @@ namespace ARM {
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AK_IWMMXT2,
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AK_XSCALE,
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AK_ARMV5E,
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AK_ARMV5TEJ,
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AK_ARMV6SM,
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AK_ARMV6J,
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AK_ARMV6HL,
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AK_ARMV7L,
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AK_ARMV7HL,
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AK_ARMV7S,
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AK_ARMV7EM,
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AK_LAST
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};
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@ -133,8 +133,8 @@ public:
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// Information by ID
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static const char * getFPUName(unsigned FPUKind);
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static const char * getArchName(unsigned ArchKind);
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static unsigned getArchDefaultCPUArch(unsigned ArchKind);
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static const char * getArchDefaultCPUName(unsigned ArchKind);
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static unsigned getArchAttr(unsigned ArchKind);
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static const char * getCPUAttr(unsigned ArchKind);
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static const char * getArchExtName(unsigned ArchExtKind);
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static const char * getDefaultCPU(StringRef Arch);
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@ -43,48 +43,51 @@ struct {
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{ "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
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{ "softvfp", ARM::FK_SOFTVFP }
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};
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// List of canonical arch names (use getArchSynonym)
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// List of canonical arch names (use getArchSynonym).
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// This table also provides the build attribute fields for CPU arch
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// and Arch ID, according to the Addenda to the ARM ABI, chapters
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// 2.4 and 2.3.5.2 respectively.
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// FIXME: TableGen this.
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struct {
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const char *Name;
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ARM::ArchKind ID;
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const char *DefaultCPU;
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ARMBuildAttrs::CPUArch DefaultArch;
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const char *CPUAttr; // CPU class in build attributes.
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ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
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} ARCHNames[] = {
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{ "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
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{ "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
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{ "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::Pre_v4 },
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{ "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
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{ "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
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{ "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5", ARM::AK_ARMV5, "5T", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
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{ "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", ARMBuildAttrs::CPUArch::v5TEJ },
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{ "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
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{ "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
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{ "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
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{ "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv6s-m", ARM::AK_ARMV6SM, "6S-M", ARMBuildAttrs::CPUArch::v6S_M },
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{ "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
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{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
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{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
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// Non-standard Arch names.
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{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
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{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
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{ "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv5e", ARM::AK_ARMV5E, "5TE", ARMBuildAttrs::CPUArch::v5TE },
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{ "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
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{ "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M },
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{ "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
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{ "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7hl", ARM::AK_ARMV7HL, "7H-L", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7hl", ARM::AK_ARMV7HL, "7-L", ARMBuildAttrs::CPUArch::v7 },
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{ "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 }
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};
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// List of canonical ARCH names (use getARCHSynonym)
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@ -211,16 +214,16 @@ const char *ARMTargetParser::getArchName(unsigned ArchKind) {
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return ARCHNames[ArchKind].Name;
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}
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const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
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const char *ARMTargetParser::getCPUAttr(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return nullptr;
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return ARCHNames[ArchKind].DefaultCPU;
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return ARCHNames[ArchKind].CPUAttr;
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}
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unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
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unsigned ARMTargetParser::getArchAttr(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return ARMBuildAttrs::CPUArch::Pre_v4;
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return ARCHNames[ArchKind].DefaultArch;
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return ARCHNames[ArchKind].ArchAttr;
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}
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const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
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@ -266,6 +269,7 @@ StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
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StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
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return StringSwitch<StringRef>(Arch)
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.Cases("armv6sm", "v6sm", "armv6s-m")
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.Cases("armv6m", "v6m", "armv6-m")
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.Cases("armv7a", "v7a", "armv7-a")
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.Cases("armv7r", "v7r", "armv7-r")
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@ -688,16 +688,16 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() {
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using namespace ARMBuildAttrs;
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setAttributeItem(CPU_name,
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ARMTargetParser::getArchDefaultCPUName(Arch),
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ARMTargetParser::getCPUAttr(Arch),
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false);
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if (EmittedArch == ARM::AK_INVALID)
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setAttributeItem(CPU_arch,
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ARMTargetParser::getArchDefaultCPUArch(Arch),
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ARMTargetParser::getArchAttr(Arch),
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false);
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else
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setAttributeItem(CPU_arch,
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ARMTargetParser::getArchDefaultCPUArch(EmittedArch),
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ARMTargetParser::getArchAttr(EmittedArch),
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false);
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switch (Arch) {
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@ -20,7 +20,7 @@
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: CPU_arch
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@ CHECK-ATTR: Description: ARM v4
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@ CHECK-ATTR: Description: Pre-v4
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: ARM_ISA_use
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@ -20,7 +20,7 @@
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: CPU_arch
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@ CHECK-ATTR: Description: ARM v4
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@ CHECK-ATTR: Description: Pre-v4
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: ARM_ISA_use
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@ -20,7 +20,7 @@
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: CPU_arch
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@ CHECK-ATTR: Description: ARM v4
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@ CHECK-ATTR: Description: Pre-v4
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: ARM_ISA_use
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@ -20,7 +20,7 @@
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: CPU_arch
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@ CHECK-ATTR: Description: ARM v4
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@ CHECK-ATTR: Description: Pre-v4
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@ CHECK-ATTR: }
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@ CHECK-ATTR: Attribute {
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@ CHECK-ATTR: TagName: ARM_ISA_use
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