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[X86] Don't accidentally select shll $1, %eax when shrinking an immediate.

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addl has higher throughput and this was needlessly picking a suboptimal
encoding causing PR23098.

I wish there was a way of doing this without further duplicating tbl-
generated patterns, but so far I haven't found one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233832 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2015-04-01 19:01:09 +00:00
parent 5436372079
commit a066ed09db
2 changed files with 29 additions and 1 deletions
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7
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@@ -2187,7 +2187,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0) if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
break; break;
unsigned ShlOp, Op; unsigned ShlOp, AddOp, Op;
MVT CstVT = NVT; MVT CstVT = NVT;
// Check the minimum bitwidth for the new constant. // Check the minimum bitwidth for the new constant.
@@ -2208,6 +2208,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
case MVT::i32: case MVT::i32:
assert(CstVT == MVT::i8); assert(CstVT == MVT::i8);
ShlOp = X86::SHL32ri; ShlOp = X86::SHL32ri;
AddOp = X86::ADD32rr;
switch (Opcode) { switch (Opcode) {
default: llvm_unreachable("Impossible opcode"); default: llvm_unreachable("Impossible opcode");
@@ -2219,6 +2220,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
case MVT::i64: case MVT::i64:
assert(CstVT == MVT::i8 || CstVT == MVT::i32); assert(CstVT == MVT::i8 || CstVT == MVT::i32);
ShlOp = X86::SHL64ri; ShlOp = X86::SHL64ri;
AddOp = X86::ADD64rr;
switch (Opcode) { switch (Opcode) {
default: llvm_unreachable("Impossible opcode"); default: llvm_unreachable("Impossible opcode");
@@ -2232,6 +2234,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
// Emit the smaller op and the shift. // Emit the smaller op and the shift.
SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT); SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst); SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
if (ShlVal == 1)
return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
SDValue(New, 0));
return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0), return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
getI8Imm(ShlVal)); getI8Imm(ShlVal));
} }

23
test/CodeGen/X86/narrow-shl-cst.ll
View File

@@ -99,3 +99,26 @@ define i64 @test11(i64 %x) nounwind {
; CHECK: xorq $-65536 ; CHECK: xorq $-65536
; CHECK: shlq $33 ; CHECK: shlq $33
} }
; PR23098
define i32 @test12(i32 %x, i32* %y) nounwind {
%and = shl i32 %x, 1
%shl = and i32 %and, 255
store i32 %shl, i32* %y
ret i32 %shl
; CHECK-LABEL: test12:
; CHECK: andl $127
; CHECK-NEXT: addl
; CHECK-NOT: shl
}
define i64 @test13(i64 %x, i64* %y) nounwind {
%and = shl i64 %x, 1
%shl = and i64 %and, 255
store i64 %shl, i64* %y
ret i64 %shl
; CHECK-LABEL: test13:
; CHECK: andq $127
; CHECK-NEXT: addq
; CHECK-NOT: shl
}