From a06cf82a7b6cbfce77d4449f2c9933dc332adcf0 Mon Sep 17 00:00:00 2001 From: Nick Lewycky Date: Tue, 30 Sep 2008 06:08:34 +0000 Subject: [PATCH] Fix misoptimization of: xor i1 (icmp eq (X, C1), icmp s[lg]t (X, C2)) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56834 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Transforms/Scalar/InstructionCombining.cpp | 5 +++-- test/Transforms/InstCombine/2008-09-29-FoldingOr.ll | 10 ++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) create mode 100644 test/Transforms/InstCombine/2008-09-29-FoldingOr.ll diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index 9023db7d508..6cac395405b 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -3023,7 +3023,7 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) { I.setOperand(1, RHSNeg); return &I; } - + // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a urem. if (I.getType()->isInteger()) { @@ -4205,7 +4205,8 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) { // Ensure that the larger constant is on the RHS. ICmpInst *LHS = cast(Op0); bool NeedsSwap; - if (ICmpInst::isSignedPredicate(LHSCC)) + if (ICmpInst::isEquality(LHSCC) ? ICmpInst::isSignedPredicate(RHSCC) + : ICmpInst::isSignedPredicate(LHSCC)) NeedsSwap = LHSCst->getValue().sgt(RHSCst->getValue()); else NeedsSwap = LHSCst->getValue().ugt(RHSCst->getValue()); diff --git a/test/Transforms/InstCombine/2008-09-29-FoldingOr.ll b/test/Transforms/InstCombine/2008-09-29-FoldingOr.ll new file mode 100644 index 00000000000..e7a8ca9b521 --- /dev/null +++ b/test/Transforms/InstCombine/2008-09-29-FoldingOr.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {or i1} +; PR2844 + +define i32 @test(i32 %p_74) { + %A = icmp eq i32 %p_74, 0 ; [#uses=1] + %B = icmp slt i32 %p_74, -638208501 ; [#uses=1] + %or.cond = or i1 %A, %B ; [#uses=1] + %iftmp.10.0 = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %iftmp.10.0 +}