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Use llvm streams instead of <iostream>

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2006-11-28 22:48:48 +00:00
parent 3e3bcbf3a0
commit a09362eb97
3 changed files with 18 additions and 20 deletions
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4
lib/CodeGen/MachineInstr.cpp
View File

@ -17,8 +17,8 @@
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/MRegisterInfo.h"
#include "llvm/Support/LeakDetector.h" #include "llvm/Support/LeakDetector.h"
#include "llvm/Support/Streams.h"
#include <iostream> #include <iostream>
using namespace llvm; using namespace llvm;
// Global variable holding an array of descriptors for machine instructions. // Global variable holding an array of descriptors for machine instructions.
@ -175,7 +175,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
} }
void MachineInstr::dump() const { void MachineInstr::dump() const {
std::cerr << " " << *this; llvm_cerr << " " << *this;
} }
static inline void OutputReg(std::ostream &os, unsigned RegNo, static inline void OutputReg(std::ostream &os, unsigned RegNo,

11
lib/CodeGen/RegAllocSimple.cpp
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@ -190,9 +190,9 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (op.isRegister() && op.getReg() && if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) { MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg(); unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n"); DOUT << "op: " << op << "\n";
DEBUG(std::cerr << "\t inst[" << i << "]: "; DOUT << "\t inst[" << i << "]: ";
MI->print(std::cerr, TM)); DEBUG(MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical // make sure the same virtual register maps to the same physical
// register in any given instruction // register in any given instruction
@ -221,8 +221,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
} }
MI->getOperand(i).setReg(physReg); MI->getOperand(i).setReg(physReg);
DEBUG(std::cerr << "virt: " << virtualReg << DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
", phys: " << op.getReg() << "\n");
} }
} }
RegClassIdx.clear(); RegClassIdx.clear();
@ -234,7 +233,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
/// runOnMachineFunction - Register allocate the whole function /// runOnMachineFunction - Register allocate the whole function
/// ///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
DEBUG(std::cerr << "Machine Function " << "\n"); DOUT << "Machine Function\n";
MF = &Fn; MF = &Fn;
TM = &MF->getTarget(); TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo(); RegInfo = TM->getRegisterInfo();

23
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -77,7 +77,7 @@ void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
/// operands. /// operands.
/// ///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(std::cerr << "Machine Function\n"); DOUT << "Machine Function\n";
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo(); const MRegisterInfo &MRI = *TM.getRegisterInfo();
const TargetInstrInfo &TII = *TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
@ -85,9 +85,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
bool MadeChange = false; bool MadeChange = false;
DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n"); DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
DEBUG(std::cerr << "********** Function: " DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
<< MF.getFunction()->getName() << '\n');
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
@ -103,7 +102,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
if (FirstTied) { if (FirstTied) {
++NumTwoAddressInstrs; ++NumTwoAddressInstrs;
DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); DOUT << '\t'; DEBUG(mi->print(std::cerr, &TM));
} }
FirstTied = false; FirstTied = false;
@ -151,12 +150,12 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
"Not a proper commutative instruction!"); "Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg(); unsigned regC = mi->getOperand(3-si).getReg();
if (LV.KillsRegister(mi, regC)) { if (LV.KillsRegister(mi, regC)) {
DEBUG(std::cerr << "2addr: COMMUTING : " << *mi); DOUT << "2addr: COMMUTING : " << *mi;
MachineInstr *NewMI = TII.commuteInstruction(mi); MachineInstr *NewMI = TII.commuteInstruction(mi);
if (NewMI == 0) { if (NewMI == 0) {
DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n"); DOUT << "2addr: COMMUTING FAILED!\n";
} else { } else {
DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI); DOUT << "2addr: COMMUTED TO: " << *NewMI;
// If the instruction changed to commute it, update livevar. // If the instruction changed to commute it, update livevar.
if (NewMI != mi) { if (NewMI != mi) {
LV.instructionChanged(mi, NewMI); // Update live variables LV.instructionChanged(mi, NewMI); // Update live variables
@ -184,8 +183,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
#endif #endif
if (MachineInstr *New = TII.convertToThreeAddress(mi)) { if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New); DOUT << "2addr: TO 3-ADDR: " << *New;
LV.instructionChanged(mi, New); // Update live variables LV.instructionChanged(mi, New); // Update live variables
mbbi->insert(mi, New); // Insert the new inst mbbi->insert(mi, New); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst. mbbi->erase(mi); // Nuke the old inst.
@ -201,7 +200,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
MachineBasicBlock::iterator prevMi = prior(mi); MachineBasicBlock::iterator prevMi = prior(mi);
DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM)); DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(std::cerr, &TM));
// Update live variables for regA // Update live variables for regA
LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
@ -226,7 +225,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi->getOperand(ti).setReg(mi->getOperand(si).getReg()); mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
MadeChange = true; MadeChange = true;
DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM)); DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(std::cerr, &TM));
} }
} }
} }