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Make the register scavenger update the bookkeeping values for sub/super

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registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47861 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2008-03-03 22:12:25 +00:00
parent 988a5782d3
commit a0a570cec6
1 changed files with 39 additions and 3 deletions
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42
lib/CodeGen/RegisterScavenging.cpp
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@@ -25,6 +25,24 @@
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
using namespace llvm; using namespace llvm;
/// setUsed - Set the register and its sub-registers as being used.
void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg);
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.reset(SubReg);
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg) {
RegsAvailable.set(Reg);
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.set(SubReg);
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
const MachineFunction &MF = *mbb->getParent(); const MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
@@ -105,9 +123,10 @@ void RegScavenger::forward() {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isUse()) if (!MO.isRegister() || !MO.isUse())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) if (Reg == 0) continue;
continue;
if (!isUsed(Reg)) { if (!isUsed(Reg)) {
// Register has been scavenged. Restore it! // Register has been scavenged. Restore it!
if (Reg != ScavengedReg) if (Reg != ScavengedReg)
@@ -115,9 +134,16 @@ void RegScavenger::forward() {
else else
restoreScavengedReg(); restoreScavengedReg();
} }
if (MO.isKill() && !isReserved(Reg))
if (MO.isKill() && !isReserved(Reg)) {
ChangedRegs.set(Reg); ChangedRegs.set(Reg);
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
ChangedRegs.set(SubReg);
}
} }
// Change states of all registers after all the uses are processed to guard // Change states of all registers after all the uses are processed to guard
// against multiple uses. // against multiple uses.
setUnused(ChangedRegs); setUnused(ChangedRegs);
@@ -125,19 +151,24 @@ void RegScavenger::forward() {
// Process defs. // Process defs.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef()) if (!MO.isRegister() || !MO.isDef())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free. // If it's dead upon def, then it is now free.
if (MO.isDead()) { if (MO.isDead()) {
setUnused(Reg); setUnused(Reg);
continue; continue;
} }
// Skip two-address destination operand. // Skip two-address destination operand.
if (TID.findTiedToSrcOperand(i) != -1) { if (TID.findTiedToSrcOperand(i) != -1) {
assert(isUsed(Reg) && "Using an undefined register!"); assert(isUsed(Reg) && "Using an undefined register!");
continue; continue;
} }
assert((isUnused(Reg) || isReserved(Reg)) && assert((isUnused(Reg) || isReserved(Reg)) &&
"Re-defining a live register!"); "Re-defining a live register!");
setUsed(Reg); setUsed(Reg);
@@ -177,6 +208,11 @@ void RegScavenger::backward() {
continue; continue;
assert(isUnused(Reg) || isReserved(Reg)); assert(isUnused(Reg) || isReserved(Reg));
ChangedRegs.set(Reg); ChangedRegs.set(Reg);
// Set the sub-registers as "used".
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
ChangedRegs.set(SubReg);
} }
setUsed(ChangedRegs); setUsed(ChangedRegs);
} }