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Optimize comparison against 0 in conditional instructions.
Fix a couple of 80-column violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145159 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wesley Peck
parent
2e38cf961d
commit
a0aa45c759
@ -751,6 +751,56 @@ def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>;
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def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
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// SET_CC operations
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETEQ),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 1)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETNE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 2)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 3)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 4)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 5)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETLE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$L, 6)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU (i32 R0), GPR:$L), 3)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU (i32 R0), GPR:$L), 4)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETUGE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU (i32 R0), GPR:$L), 5)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 0), SETULE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU (i32 R0), GPR:$L), 6)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETEQ),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 1)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETNE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 2)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETGT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 3)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 4)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETGE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 5)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETLE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), GPR:$R, 6)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETUGT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU GPR:$R, (i32 R0)), 3)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETULT),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU GPR:$R, (i32 R0)), 4)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETUGE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU GPR:$R, (i32 R0)), 5)>;
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def : Pat<(setcc (i32 0), (i32 GPR:$R), SETULE),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMPU GPR:$R, (i32 R0)), 6)>;
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def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
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(Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
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(CMP GPR:$R, GPR:$L), 1)>;
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@ -787,6 +837,68 @@ def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)),
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(Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>;
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// SELECT_CC
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETEQ),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 1)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETNE),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 2)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETGT),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 3)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETLT),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 4)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETGE),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 5)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETLE),
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(Select_CC GPR:$T, GPR:$F, GPR:$L, 6)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETUGT),
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(Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 3)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETULT),
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(Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 4)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETUGE),
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(Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 5)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 0),
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(i32 GPR:$T), (i32 GPR:$F), SETULE),
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(Select_CC GPR:$T, GPR:$F, (CMPU (i32 R0), GPR:$L), 6)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETEQ),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 1)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETNE),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 2)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETGT),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 3)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETLT),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 4)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETGE),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 5)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETLE),
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(Select_CC GPR:$T, GPR:$F, GPR:$R, 6)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETUGT),
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(Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 3)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETULT),
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(Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 4)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETUGE),
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(Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 5)>;
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def : Pat<(selectcc (i32 0), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETULE),
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(Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, (i32 R0)), 6)>;
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def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R),
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(i32 GPR:$T), (i32 GPR:$F), SETEQ),
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(Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 1)>;
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@ -827,6 +939,48 @@ def : Pat<(br bb:$T), (BRID bb:$T)>;
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def : Pat<(brind GPR:$T), (BRAD GPR:$T)>;
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// BRCOND instructions
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETEQ), bb:$T),
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(BEQID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETNE), bb:$T),
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(BNEID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETGT), bb:$T),
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(BGTID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLT), bb:$T),
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(BLTID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETGE), bb:$T),
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(BGEID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETLE), bb:$T),
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(BLEID GPR:$L, bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETUGT), bb:$T),
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(BGTID (CMPU (i32 R0), GPR:$L), bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETULT), bb:$T),
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(BLTID (CMPU (i32 R0), GPR:$L), bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETUGE), bb:$T),
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(BGEID (CMPU (i32 R0), GPR:$L), bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETULE), bb:$T),
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(BLEID (CMPU (i32 R0), GPR:$L), bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETEQ), bb:$T),
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(BEQID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETNE), bb:$T),
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(BNEID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETGT), bb:$T),
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(BGTID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLT), bb:$T),
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(BLTID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETGE), bb:$T),
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(BGEID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETLE), bb:$T),
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(BLEID GPR:$R, bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETUGT), bb:$T),
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(BGTID (CMPU GPR:$R, (i32 R0)), bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETULT), bb:$T),
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(BLTID (CMPU GPR:$R, (i32 R0)), bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETUGE), bb:$T),
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(BGEID (CMPU GPR:$R, (i32 R0)), bb:$T)>;
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def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETULE), bb:$T),
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(BLEID (CMPU GPR:$R, (i32 R0)), bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T),
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(BEQID (CMP GPR:$R, GPR:$L), bb:$T)>;
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def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
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@ -869,11 +1023,11 @@ def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
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def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
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// 16-bit load and store
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def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>;
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def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$ad), (SH GPR:$dst, xaddr:$ad)>;
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def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>;
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// 8-bit load and store
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def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>;
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def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$ad), (SB GPR:$dst, xaddr:$ad)>;
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def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>;
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// Peepholes
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