mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[FastISel][AArch64] Fold sign-/zero-extends into the load instruction.
The sign-/zero-extension of the loaded value can be performed by the memory instruction for free. If the result of the load has only one use and the use is a sign-/zero-extend, then we emit the proper load instruction. The extend is only a register copy and will be optimized away later on. Other instructions that consume the sign-/zero-extended value are also made aware of this fact, so they don't fold the extend too. This fixes rdar://problem/18495928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218653 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
e8a9706eda
commit
a0af4b0271
@ -177,7 +177,7 @@ private:
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bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
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bool emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool emitLoad(MVT VT, unsigned &ResultReg, Address Addr, bool WantZExt = true,
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MachineMemOperand *MMO = nullptr);
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bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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@ -255,6 +255,23 @@ public:
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#include "AArch64GenCallingConv.inc"
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/// \brief Check if the sign-/zero-extend will be a noop.
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static bool isIntExtFree(const Instruction *I) {
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assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
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"Unexpected integer extend instruction.");
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bool IsZExt = isa<ZExtInst>(I);
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if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0)))
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if (LI->hasOneUse())
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return true;
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if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0)))
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if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
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return true;
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return false;
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}
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/// \brief Determine the implicit scale factor that is applied by a memory
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/// operation for a given value type.
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static unsigned getImplicitScaleFactor(MVT VT) {
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@ -585,72 +602,74 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
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if (Addr.getOffsetReg())
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break;
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if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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unsigned Val = CI->getZExtValue();
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if (Val < 1 || Val > 3)
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break;
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const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1));
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if (!CI)
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break;
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uint64_t NumBytes = 0;
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if (Ty && Ty->isSized()) {
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uint64_t NumBits = DL.getTypeSizeInBits(Ty);
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NumBytes = NumBits / 8;
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if (!isPowerOf2_64(NumBits))
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NumBytes = 0;
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}
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unsigned Val = CI->getZExtValue();
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if (Val < 1 || Val > 3)
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break;
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if (NumBytes != (1ULL << Val))
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break;
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uint64_t NumBytes = 0;
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if (Ty && Ty->isSized()) {
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uint64_t NumBits = DL.getTypeSizeInBits(Ty);
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NumBytes = NumBits / 8;
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if (!isPowerOf2_64(NumBits))
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NumBytes = 0;
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}
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Addr.setShift(Val);
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Addr.setExtendType(AArch64_AM::LSL);
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if (NumBytes != (1ULL << Val))
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break;
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const Value *Src = U->getOperand(0);
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if (const auto *I = dyn_cast<Instruction>(Src))
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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Src = I;
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Addr.setShift(Val);
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Addr.setExtendType(AArch64_AM::LSL);
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if (const auto *ZE = dyn_cast<ZExtInst>(Src)) {
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if (ZE->getOperand(0)->getType()->isIntegerTy(32)) {
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const Value *Src = U->getOperand(0);
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if (const auto *I = dyn_cast<Instruction>(Src))
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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Src = I;
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// Fold the zext or sext when it won't become a noop.
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if (const auto *ZE = dyn_cast<ZExtInst>(Src)) {
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if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
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Addr.setExtendType(AArch64_AM::UXTW);
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Src = ZE->getOperand(0);
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}
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} else if (const auto *SE = dyn_cast<SExtInst>(Src)) {
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if (SE->getOperand(0)->getType()->isIntegerTy(32)) {
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Addr.setExtendType(AArch64_AM::SXTW);
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Src = SE->getOperand(0);
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}
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}
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} else if (const auto *SE = dyn_cast<SExtInst>(Src)) {
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if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
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Addr.setExtendType(AArch64_AM::SXTW);
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Src = SE->getOperand(0);
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}
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}
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if (const auto *AI = dyn_cast<BinaryOperator>(Src))
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if (AI->getOpcode() == Instruction::And) {
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const Value *LHS = AI->getOperand(0);
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const Value *RHS = AI->getOperand(1);
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if (const auto *C = dyn_cast<ConstantInt>(LHS))
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if (C->getValue() == 0xffffffff)
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std::swap(LHS, RHS);
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if (const auto *C = dyn_cast<ConstantInt>(RHS))
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if (C->getValue() == 0xffffffff) {
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Addr.setExtendType(AArch64_AM::UXTW);
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unsigned Reg = getRegForValue(LHS);
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if (!Reg)
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return false;
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bool RegIsKill = hasTrivialKill(LHS);
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Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
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AArch64::sub_32);
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Addr.setOffsetReg(Reg);
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return true;
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}
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}
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if (const auto *AI = dyn_cast<BinaryOperator>(Src))
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if (AI->getOpcode() == Instruction::And) {
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const Value *LHS = AI->getOperand(0);
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const Value *RHS = AI->getOperand(1);
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if (const auto *C = dyn_cast<ConstantInt>(LHS))
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if (C->getValue() == 0xffffffff)
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std::swap(LHS, RHS);
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if (const auto *C = dyn_cast<ConstantInt>(RHS))
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if (C->getValue() == 0xffffffff) {
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Addr.setExtendType(AArch64_AM::UXTW);
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unsigned Reg = getRegForValue(LHS);
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if (!Reg)
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return false;
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bool RegIsKill = hasTrivialKill(LHS);
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Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
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AArch64::sub_32);
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Addr.setOffsetReg(Reg);
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return true;
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}
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}
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unsigned Reg = getRegForValue(Src);
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if (!Reg)
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return false;
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Addr.setOffsetReg(Reg);
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return true;
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}
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break;
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unsigned Reg = getRegForValue(Src);
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if (!Reg)
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return false;
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Addr.setOffsetReg(Reg);
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return true;
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}
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case Instruction::Mul: {
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if (Addr.getOffsetReg())
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@ -692,13 +711,15 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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Src = I;
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// Fold the zext or sext when it won't become a noop.
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if (const auto *ZE = dyn_cast<ZExtInst>(Src)) {
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if (ZE->getOperand(0)->getType()->isIntegerTy(32)) {
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if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
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Addr.setExtendType(AArch64_AM::UXTW);
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Src = ZE->getOperand(0);
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}
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} else if (const auto *SE = dyn_cast<SExtInst>(Src)) {
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if (SE->getOperand(0)->getType()->isIntegerTy(32)) {
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if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
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Addr.setExtendType(AArch64_AM::SXTW);
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Src = SE->getOperand(0);
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}
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@ -1568,7 +1589,7 @@ unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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}
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bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO) {
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bool WantZExt, MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!simplifyAddress(Addr, VT))
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return false;
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@ -1585,20 +1606,38 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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ScaleFactor = 1;
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}
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static const unsigned OpcTable[4][6] = {
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{ AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
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AArch64::LDURSi, AArch64::LDURDi },
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{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
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AArch64::LDRSui, AArch64::LDRDui },
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{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
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AArch64::LDRSroX, AArch64::LDRDroX },
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{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
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AArch64::LDRSroW, AArch64::LDRDroW }
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static const unsigned GPOpcTable[2][4][4] = {
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// Sign-extend.
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{ { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURSWi,
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AArch64::LDURXi },
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{ AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRSWui,
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AArch64::LDRXui },
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{ AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRSWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRSWroW,
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AArch64::LDRXroW },
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},
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// Zero-extend.
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{ { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
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AArch64::LDURXi },
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{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
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AArch64::LDRXui },
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{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
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AArch64::LDRXroX },
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{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
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AArch64::LDRXroW }
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}
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};
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static const unsigned FPOpcTable[4][2] = {
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{ AArch64::LDURSi, AArch64::LDURDi },
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{ AArch64::LDRSui, AArch64::LDRDui },
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{ AArch64::LDRSroX, AArch64::LDRDroX },
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{ AArch64::LDRSroW, AArch64::LDRDroW }
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};
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unsigned Opc;
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const TargetRegisterClass *RC;
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bool VTIsi1 = false;
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bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
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Addr.getOffsetReg();
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unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
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@ -1607,14 +1646,33 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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Idx++;
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switch (VT.SimpleTy) {
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default: llvm_unreachable("Unexpected value type.");
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case MVT::i1: VTIsi1 = true; // Intentional fall-through.
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case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
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case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
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case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
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case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
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case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
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case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
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default:
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llvm_unreachable("Unexpected value type.");
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case MVT::i1: // Intentional fall-through.
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case MVT::i8:
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Opc = GPOpcTable[WantZExt][Idx][0];
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RC = &AArch64::GPR32RegClass;
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break;
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case MVT::i16:
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Opc = GPOpcTable[WantZExt][Idx][1];
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RC = &AArch64::GPR32RegClass;
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break;
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case MVT::i32:
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Opc = GPOpcTable[WantZExt][Idx][2];
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RC = WantZExt ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;
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break;
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case MVT::i64:
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Opc = GPOpcTable[WantZExt][Idx][3];
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RC = &AArch64::GPR64RegClass;
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break;
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case MVT::f32:
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Opc = FPOpcTable[Idx][0];
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RC = &AArch64::FPR32RegClass;
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break;
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case MVT::f64:
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Opc = FPOpcTable[Idx][1];
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RC = &AArch64::FPR64RegClass;
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break;
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}
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// Create the base instruction, then add the operands.
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@ -1623,8 +1681,14 @@ bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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TII.get(Opc), ResultReg);
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addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
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// For 32bit loads we do sign-extending loads to 64bit and then extract the
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// subreg. In the end this is just a NOOP.
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if (VT == MVT::i32 && !WantZExt)
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ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, /*IsKill=*/true,
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AArch64::sub_32);
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// Loading an i1 requires special handling.
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if (VTIsi1) {
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if (VT == MVT::i1) {
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unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
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assert(ANDReg && "Unexpected AND instruction emission failure.");
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ResultReg = ANDReg;
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@ -1701,8 +1765,12 @@ bool AArch64FastISel::selectLoad(const Instruction *I) {
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if (!computeAddress(I->getOperand(0), Addr, I->getType()))
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return false;
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bool WantZExt = true;
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if (I->hasOneUse() && isa<SExtInst>(I->use_begin()->getUser()))
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WantZExt = false;
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unsigned ResultReg;
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if (!emitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
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if (!emitLoad(VT, ResultReg, Addr, WantZExt, createMachineMemOperandFor(I)))
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return false;
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updateValueMap(I, ResultReg);
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@ -3776,46 +3844,60 @@ unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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}
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bool AArch64FastISel::selectIntExt(const Instruction *I) {
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// On ARM, in general, integer casts don't involve legal types; this code
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// handles promotable integers. The high bits for a type smaller than
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// the register size are assumed to be undefined.
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Type *DestTy = I->getType();
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
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"Unexpected integer extend instruction.");
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MVT RetVT;
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MVT SrcVT;
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if (!isTypeSupported(I->getType(), RetVT))
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
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return false;
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if (isIntExtFree(I)) {
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (!SrcReg)
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return false;
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bool SrcIsKill = hasTrivialKill(I->getOperand(0));
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const TargetRegisterClass *RC = (RetVT == MVT::i64) ?
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&AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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unsigned ResultReg = createResultReg(RC);
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if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addImm(AArch64::sub_32);
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} else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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}
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updateValueMap(I, ResultReg);
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return true;
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}
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (!SrcReg)
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return false;
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bool SrcRegIsKill = hasTrivialKill(I->getOperand(0));
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EVT SrcEVT = TLI.getValueType(SrcTy, true);
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EVT DestEVT = TLI.getValueType(DestTy, true);
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if (!SrcEVT.isSimple())
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return false;
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if (!DestEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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MVT DestVT = DestEVT.getSimpleVT();
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unsigned ResultReg = 0;
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bool IsZExt = isa<ZExtInst>(I);
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// Check if it is an argument and if it is already zero/sign-extended.
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if (const auto *Arg = dyn_cast<Argument>(Src)) {
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if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
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if (DestVT == MVT::i64) {
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ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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if (isIntExtFree(I)) {
|
||||
if (RetVT == MVT::i64) {
|
||||
ResultReg = createResultReg(&AArch64::GPR64RegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(AArch64::SUBREG_TO_REG), ResultReg)
|
||||
.addImm(0)
|
||||
.addReg(SrcReg)
|
||||
.addReg(SrcReg, getKillRegState(SrcRegIsKill))
|
||||
.addImm(AArch64::sub_32);
|
||||
} else
|
||||
ResultReg = SrcReg;
|
||||
}
|
||||
} else
|
||||
ResultReg = SrcReg;
|
||||
}
|
||||
|
||||
if (!ResultReg)
|
||||
ResultReg = emitIntExt(SrcVT, SrcReg, DestVT, IsZExt);
|
||||
ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, isa<ZExtInst>(I));
|
||||
|
||||
if (!ResultReg)
|
||||
return false;
|
||||
@ -3891,18 +3973,22 @@ bool AArch64FastISel::selectMul(const Instruction *I) {
|
||||
MVT SrcVT = VT;
|
||||
bool IsZExt = true;
|
||||
if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
|
||||
MVT VT;
|
||||
if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
|
||||
SrcVT = VT;
|
||||
IsZExt = true;
|
||||
Src0 = ZExt->getOperand(0);
|
||||
if (!isIntExtFree(ZExt)) {
|
||||
MVT VT;
|
||||
if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
|
||||
SrcVT = VT;
|
||||
IsZExt = true;
|
||||
Src0 = ZExt->getOperand(0);
|
||||
}
|
||||
}
|
||||
} else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
|
||||
MVT VT;
|
||||
if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
|
||||
SrcVT = VT;
|
||||
IsZExt = false;
|
||||
Src0 = SExt->getOperand(0);
|
||||
if (!isIntExtFree(SExt)) {
|
||||
MVT VT;
|
||||
if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
|
||||
SrcVT = VT;
|
||||
IsZExt = false;
|
||||
Src0 = SExt->getOperand(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -3954,18 +4040,22 @@ bool AArch64FastISel::selectShift(const Instruction *I) {
|
||||
bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
|
||||
const Value *Op0 = I->getOperand(0);
|
||||
if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
|
||||
MVT TmpVT;
|
||||
if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
|
||||
SrcVT = TmpVT;
|
||||
IsZExt = true;
|
||||
Op0 = ZExt->getOperand(0);
|
||||
if (!isIntExtFree(ZExt)) {
|
||||
MVT TmpVT;
|
||||
if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
|
||||
SrcVT = TmpVT;
|
||||
IsZExt = true;
|
||||
Op0 = ZExt->getOperand(0);
|
||||
}
|
||||
}
|
||||
} else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
|
||||
MVT TmpVT;
|
||||
if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
|
||||
SrcVT = TmpVT;
|
||||
IsZExt = false;
|
||||
Op0 = SExt->getOperand(0);
|
||||
if (!isIntExtFree(SExt)) {
|
||||
MVT TmpVT;
|
||||
if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
|
||||
SrcVT = TmpVT;
|
||||
IsZExt = false;
|
||||
Op0 = SExt->getOperand(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -4213,13 +4303,8 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
|
||||
case Instruction::FPToUI:
|
||||
return selectFPToInt(I, /*Signed=*/false);
|
||||
case Instruction::ZExt:
|
||||
if (!selectCast(I, ISD::ZERO_EXTEND))
|
||||
return selectIntExt(I);
|
||||
return true;
|
||||
case Instruction::SExt:
|
||||
if (!selectCast(I, ISD::SIGN_EXTEND))
|
||||
return selectIntExt(I);
|
||||
return true;
|
||||
return selectIntExt(I);
|
||||
case Instruction::Trunc:
|
||||
if (!selectCast(I, ISD::TRUNCATE))
|
||||
return selectTrunc(I);
|
||||
|
||||
@ -17,7 +17,6 @@ entry:
|
||||
; CHECK: ldrh w0, [sp, #12]
|
||||
; CHECK: strb w0, [sp, #15]
|
||||
; CHECK: ldrb w0, [sp, #15]
|
||||
; CHECK: uxtb w0, w0
|
||||
; CHECK: add sp, sp, #16
|
||||
; CHECK: ret
|
||||
%a.addr = alloca i8, align 1
|
||||
@ -51,14 +50,11 @@ entry:
|
||||
; CHECK: str w2, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrb w0, [sp, #15]
|
||||
; CHECK: uxtb w0, w0
|
||||
; CHECK: strh w0, [sp, #12]
|
||||
; CHECK: ldrh w0, [sp, #12]
|
||||
; CHECK: uxth w0, w0
|
||||
; CHECK: str w0, [sp, #8]
|
||||
; CHECK: ldr w0, [sp, #8]
|
||||
; CHECK: mov x3, x0
|
||||
; CHECK: ubfx x3, x3, #0, #32
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldr x0, [sp]
|
||||
; CHECK: ret
|
||||
@ -109,15 +105,11 @@ entry:
|
||||
; CHECK: strh w1, [sp, #12]
|
||||
; CHECK: str w2, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrb w0, [sp, #15]
|
||||
; CHECK: sxtb w0, w0
|
||||
; CHECK: ldrsb w0, [sp, #15]
|
||||
; CHECK: strh w0, [sp, #12]
|
||||
; CHECK: ldrh w0, [sp, #12]
|
||||
; CHECK: sxth w0, w0
|
||||
; CHECK: ldrsh w0, [sp, #12]
|
||||
; CHECK: str w0, [sp, #8]
|
||||
; CHECK: ldr w0, [sp, #8]
|
||||
; CHECK: mov x3, x0
|
||||
; CHECK: sxtw x3, w3
|
||||
; CHECK: ldrsw x3, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldr x0, [sp]
|
||||
; CHECK: ret
|
||||
|
||||
190
test/CodeGen/AArch64/fast-isel-int-ext.ll
Normal file
190
test/CodeGen/AArch64/fast-isel-int-ext.ll
Normal file
@ -0,0 +1,190 @@
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
;
|
||||
; Test that we only use the sign/zero extend in the address calculation when
|
||||
; necessary.
|
||||
;
|
||||
; SHIFT
|
||||
;
|
||||
define i64 @load_addr_shift_zext1(i32 zeroext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_shift_zext1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = shl i64 %1, 3
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_shift_zext2(i32 signext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_shift_zext2
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3{{\]}}
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = shl i64 %1, 3
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_shift_sext1(i32 signext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_shift_sext1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = shl i64 %1, 3
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_shift_sext2(i32 zeroext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_shift_sext2
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = shl i64 %1, 3
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
;
|
||||
; MUL
|
||||
;
|
||||
define i64 @load_addr_mul_zext1(i32 zeroext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_zext1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_mul_zext2(i32 signext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_zext2
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_mul_sext1(i32 signext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_sext1
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, x0, lsl #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
define i64 @load_addr_mul_sext2(i32 zeroext %a, i64 %b) {
|
||||
; CHECK-LABEL: load_addr_mul_sext2
|
||||
; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = mul i64 %1, 8
|
||||
%3 = add i64 %b, %2
|
||||
%4 = inttoptr i64 %3 to i64*
|
||||
%5 = load i64* %4
|
||||
ret i64 %5
|
||||
}
|
||||
|
||||
; Test folding of the sign-/zero-extend into the load instruction.
|
||||
define i32 @load_zext_i8_to_i32(i8* %a) {
|
||||
; CHECK-LABEL: load_zext_i8_to_i32
|
||||
; CHECK: ldrb w0, [x0]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = load i8* %a
|
||||
%2 = zext i8 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @load_zext_i16_to_i32(i16* %a) {
|
||||
; CHECK-LABEL: load_zext_i16_to_i32
|
||||
; CHECK: ldrh w0, [x0]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = load i16* %a
|
||||
%2 = zext i16 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @load_zext_i8_to_i64(i8* %a) {
|
||||
; CHECK-LABEL: load_zext_i8_to_i64
|
||||
; CHECK: ldrb w0, [x0]
|
||||
; CHECK-NOT: uxtb
|
||||
%1 = load i8* %a
|
||||
%2 = zext i8 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @load_zext_i16_to_i64(i16* %a) {
|
||||
; CHECK-LABEL: load_zext_i16_to_i64
|
||||
; CHECK: ldrh w0, [x0]
|
||||
; CHECK-NOT: uxth
|
||||
%1 = load i16* %a
|
||||
%2 = zext i16 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @load_zext_i32_to_i64(i32* %a) {
|
||||
; CHECK-LABEL: load_zext_i32_to_i64
|
||||
; CHECK: ldr w0, [x0]
|
||||
; CHECK-NOT: uxtw
|
||||
%1 = load i32* %a
|
||||
%2 = zext i32 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i32 @load_sext_i8_to_i32(i8* %a) {
|
||||
; CHECK-LABEL: load_sext_i8_to_i32
|
||||
; CHECK: ldrsb w0, [x0]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = load i8* %a
|
||||
%2 = sext i8 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @load_sext_i16_to_i32(i16* %a) {
|
||||
; CHECK-LABEL: load_sext_i16_to_i32
|
||||
; CHECK: ldrsh w0, [x0]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = load i16* %a
|
||||
%2 = sext i16 %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i64 @load_sext_i8_to_i64(i8* %a) {
|
||||
; CHECK-LABEL: load_sext_i8_to_i64
|
||||
; CHECK: ldrsb w0, [x0]
|
||||
; CHECK-NOT: sxtb
|
||||
%1 = load i8* %a
|
||||
%2 = sext i8 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @load_sext_i16_to_i64(i16* %a) {
|
||||
; CHECK-LABEL: load_sext_i16_to_i64
|
||||
; CHECK: ldrsh w0, [x0]
|
||||
; CHECK-NOT: sxth
|
||||
%1 = load i16* %a
|
||||
%2 = sext i16 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
define i64 @load_sext_i32_to_i64(i32* %a) {
|
||||
; CHECK-LABEL: load_sext_i32_to_i64
|
||||
; CHECK: ldrsw x0, [x0]
|
||||
; CHECK-NOT: sxtw
|
||||
%1 = load i32* %a
|
||||
%2 = sext i32 %1 to i64
|
||||
ret i64 %2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user