6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-05 13:09:10 +00:00
Code Issues Projects Releases Wiki Activity

The add/sub SP instructions are really pseudos. The assembler should ignore

Browse Source 
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-12-09 01:21:27 +00:00
parent a35cce1a14
commit a0e23c5e95
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1160,6 +1160,7 @@ def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
// add/sub instructions. In thumb1 we need them since they have dedicated
// encodings. At the least, they should be pseudo instructions.
// ADD r, sp, {so_imm|i12}
let isCodeGenOnly = 1 in {
def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
let Inst{31-27} = 0b11110;
@ -1209,6 +1210,7 @@ def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
}
} // end isCodeGenOnly = 1
// Signed and unsigned division on v7-M
def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,