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AVX-512: fixed extended load to 512-bit register

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-05-17 08:08:06 +00:00
parent 84b93666b3
commit a0eb803376
2 changed files with 12 additions and 2 deletions
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4
lib/Target/X86/X86ISelLowering.cpp
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@ -14022,8 +14022,8 @@ static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
"Can only lower sext loads with a single scalar load!");
unsigned loadRegZize = RegSz;
if (Ext == ISD::SEXTLOAD && RegSz == 256)
loadRegZize /= 2;
if (Ext == ISD::SEXTLOAD && RegSz >= 256)
loadRegZize = 128;
// Represent our vector as a sequence of elements which are the
// largest scalar that we can load.

10
test/CodeGen/X86/avx512-trunc-ext.ll
View File

@ -193,3 +193,13 @@ define <8 x i64> @sext_8i1_8i64(<8 x i32> %a1, <8 x i32> %a2) nounwind {
%y = sext <8 x i1> %x to <8 x i64>
ret <8 x i64> %y
}
; CHECK-LABEL: @extload_v8i64
; CHECK: vpmovsxbq
define void @extload_v8i64(<8 x i8>* %a, <8 x i64>* %res) {
%sign_load = load <8 x i8>, <8 x i8>* %a
%c = sext <8 x i8> %sign_load to <8 x i64>
store <8 x i64> %c, <8 x i64>* %res
ret void
}