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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8
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Evan Cheng 2007-03-20 22:32:39 +00:00
parent c3c70881cf
commit a125cbe839
1 changed files with 6 additions and 1 deletions
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7
lib/Target/ARM/README.txt
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@ -470,4 +470,9 @@ More register scavenging work:
//===---------------------------------------------------------------------===//
Teach LSR about ARM addressing modes.
More LSR enhancements possible:
1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
in a load / store.
2. Allow iv reuse even when a type conversion is required. For example, i8
and i32 load / store addressing modes are identical.