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Change the heuristics used in the coalescer, register allocator, and within

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live intervals itself to use an instruction count approximation that is 
not affected by inserting empty indices.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53937 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2008-07-22 22:46:49 +00:00
parent 38bcec13e8
commit a1566f2e12
5 changed files with 29 additions and 14 deletions
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3
lib/CodeGen/RegAllocLinearScan.cpp
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@ -851,7 +851,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
if (minWeight == HUGE_VALF) {
// All registers must have inf weight. Just grab one!
minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
if (cur->weight == HUGE_VALF || cur->getSize() == 1)
if (cur->weight == HUGE_VALF ||
li_->getApproximateInstructionCount(*cur) == 1)
// Spill a physical register around defs and uses.
li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
}