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Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-06-03 18:58:46 +00:00
parent bb6e61cf6b
commit a15f9d5311
6 changed files with 11 additions and 11 deletions
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4
lib/Target/X86/X86.td
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@ -89,7 +89,7 @@ def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
"Enable packed carry-less multiplication instructions",
[FeatureSSE2]>;
def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
"Enable three-operand fused multiple-add",
[FeatureAVX]>;
def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
@ -188,7 +188,7 @@ def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,
FeatureAES, FeaturePCLMUL, FeatureRDRAND,
FeatureF16C, FeatureFSGSBase,
FeatureMOVBE, FeatureLZCNT, FeatureBMI,
FeatureBMI2, FeatureFMA3]>;
FeatureBMI2, FeatureFMA]>;
def : Proc<"k6", [FeatureMMX]>;
def : Proc<"k6-2", [Feature3DNow]>;

2
lib/Target/X86/X86InstrFormats.td
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@ -526,7 +526,7 @@ class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
: I<o, F, outs, ins, asm, pattern, itin>, T8,
OpSize, VEX_4V, Requires<[HasFMA3]>;
OpSize, VEX_4V, Requires<[HasFMA]>;
// FMA4 Instruction Templates
class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,

2
lib/Target/X86/X86InstrInfo.td
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@ -531,7 +531,7 @@ def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
def HasAES : Predicate<"Subtarget->hasAES()">;
def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
def HasFMA : Predicate<"Subtarget->hasFMA()">;
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
def HasXOP : Predicate<"Subtarget->hasXOP()">;
def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;

6
lib/Target/X86/X86Subtarget.cpp
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@ -206,8 +206,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
ToggleFeature(X86::FeaturePCLMUL);
}
if ((ECX >> 12) & 0x1) {
HasFMA3 = true;
ToggleFeature(X86::FeatureFMA3);
HasFMA = true;
ToggleFeature(X86::FeatureFMA);
}
if (IsIntel && ((ECX >> 22) & 0x1)) {
HasMOVBE = true;
@ -327,7 +327,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
, HasSSE4A(false)
, HasAES(false)
, HasPCLMUL(false)
, HasFMA3(false)
, HasFMA(false)
, HasFMA4(false)
, HasXOP(false)
, HasMOVBE(false)

6
lib/Target/X86/X86Subtarget.h
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@ -88,8 +88,8 @@ protected:
/// HasPCLMUL - Target has carry-less multiplication
bool HasPCLMUL;
/// HasFMA3 - Target has 3-operand fused multiply-add
bool HasFMA3;
/// HasFMA - Target has 3-operand fused multiply-add
bool HasFMA;
/// HasFMA4 - Target has 4-operand fused multiply-add
bool HasFMA4;
@ -204,7 +204,7 @@ public:
bool hasPOPCNT() const { return HasPOPCNT; }
bool hasAES() const { return HasAES; }
bool hasPCLMUL() const { return HasPCLMUL; }
bool hasFMA3() const { return HasFMA3; }
bool hasFMA() const { return HasFMA; }
bool hasFMA4() const { return HasFMA4; }
bool hasXOP() const { return HasXOP; }
bool hasMOVBE() const { return HasMOVBE; }

2
test/CodeGen/X86/fma3-intrinsics.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=core-avx2 -mattr=avx2,+fma3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=core-avx2 -mattr=avx2,+fma | FileCheck %s
define <4 x float> @test_x86_fmadd_ss(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
; CHECK: fmadd132ss %xmm