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The enabling of remat in 2-address conversion breaks this test:

Browse Source 
Running /Users/void/llvm/llvm.src/test/CodeGen/X86/dg.exp ...
FAIL: /Users/void/llvm/llvm.src/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
Failed with exit(1) at line 1
while running: llvm-as < /Users/void/llvm/llvm.src/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll | llc -march=x86 -mattr=+sse2 -stats |&  grep {1 .*folded into instructions}
child process exited abnormally

Make this conditional for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-05-26 05:49:49 +00:00
parent 48f7f237ea
commit a16157a410
1 changed files with 29 additions and 22 deletions
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51
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -37,6 +37,7 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/SmallPtrSet.h"
@ -49,6 +50,10 @@ STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
static cl::opt<bool>
EnableReMat("2-addr-remat", cl::init(false), cl::Hidden,
cl::desc("Two-addr conversion should remat when possible."));
namespace {
class VISIBILITY_HIDDEN TwoAddressInstructionPass
: public MachineFunctionPass {
@ -326,7 +331,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
MachineInstr *Orig = MRI->getVRegDef(regB);
if (Orig && TII->isTriviallyReMaterializable(Orig)) {
if (EnableReMat && Orig && TII->isTriviallyReMaterializable(Orig)) {
TII->reMaterialize(*mbbi, mi, regA, Orig);
ReMattedInstrs.insert(Orig);
} else {
@ -367,33 +372,35 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
}
}
SmallPtrSet<MachineInstr*, 8>::iterator I = ReMattedInstrs.begin();
SmallPtrSet<MachineInstr*, 8>::iterator E = ReMattedInstrs.end();
if (EnableReMat) {
SmallPtrSet<MachineInstr*, 8>::iterator I = ReMattedInstrs.begin();
SmallPtrSet<MachineInstr*, 8>::iterator E = ReMattedInstrs.end();
for (; I != E; ++I) {
MachineInstr *MI = *I;
bool InstrDead = true;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister())
continue;
unsigned MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isDef()) {
if (MO.isImplicit())
for (; I != E; ++I) {
MachineInstr *MI = *I;
bool InstrDead = true;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister())
continue;
unsigned MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isDef()) {
if (MO.isImplicit())
continue;
if (MRI->use_begin(MOReg) != MRI->use_end()) {
InstrDead = false;
break;
if (MRI->use_begin(MOReg) != MRI->use_end()) {
InstrDead = false;
break;
}
}
}
}
if (InstrDead && MI->getNumOperands() > 0)
MI->eraseFromParent();
if (InstrDead && MI->getNumOperands() > 0)
MI->eraseFromParent();
}
}
return MadeChange;