From a1719c91309c21e7edd0f72c07592fc309143a9a Mon Sep 17 00:00:00 2001 From: Brian Gaeke Date: Thu, 31 Oct 2002 23:03:59 +0000 Subject: [PATCH] InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst. Add ISel::visitShiftInst() to instruction select shift instructions. Add a comment in visitAdd about how to do 64 bit adds. X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/InstSelectSimple.cpp | 189 +++++++++++++++++++++++++++- lib/Target/X86/X86ISelSimple.cpp | 189 +++++++++++++++++++++++++++- lib/Target/X86/X86InstrInfo.def | 28 ++++- 3 files changed, 401 insertions(+), 5 deletions(-) diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index d0d80e3226c..7e4f689fe2a 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -8,6 +8,7 @@ #include "X86InstrInfo.h" #include "llvm/Function.h" #include "llvm/iTerminators.h" +#include "llvm/iOther.h" #include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/Pass.h" @@ -55,6 +56,7 @@ namespace { // void visitReturnInst(ReturnInst &RI); void visitAdd(BinaryOperator &B); + void visitShiftInst(ShiftInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; @@ -141,6 +143,186 @@ void ISel::visitReturnInst(ReturnInst &I) { BuildMI(BB, X86::RET, 0); } +/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here +/// for constant immediate shift values, and for constant immediate +/// shift values equal to 1. Even the general case is sort of special, +/// because the shift amount has to be in CL, not just any old register. +/// +void +ISel::visitShiftInst (ShiftInst & I) +{ + unsigned Op0r = getReg (I.getOperand (0)); + unsigned DestReg = getReg (I); + unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize (); + bool isRightShift = (I.getOpcode () == Instruction::Shr); + bool isOperandUnsigned = I.getType ()->isUnsigned (); + bool isConstantShiftAmount = (isa (I.getOperand (1))); + if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) + { + // The shift amount is constant. Get its value. + uint64_t shAmt = CUI->getValue (); + // Emit: reg, shamt (shift-by-immediate opcode "ir" form.) + if (isRightShift) + { + if (isOperandUnsigned) + { + // This is a shift right logical (SHR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHRir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SHRir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SHRir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + else + { + // This is a shift right arithmetic (SAR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SARir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SARir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SARir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // This is a left shift (SHL). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHLir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SHLir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SHLir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // The shift amount is non-constant. + // + // In fact, you can only shift with a variable shift amount if + // that amount is already in the CL register, so we have to put it + // there first. + // + // Get it from the register it's in. + unsigned Op1r = getReg (I.getOperand (1)); + // Emit: move cl, shiftAmount (put the shift amount in CL.) + BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r); + // Emit: reg, cl (shift-by-CL opcode; "rr" form.) + if (isRightShift) + { + if (isOperandUnsigned) + { + // This is a shift right logical (SHR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHRrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SHRrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SHRrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + else + { + // This is a shift right arithmetic (SAR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SARrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SARrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SARrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // This is a left shift (SHL). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHLrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SHLrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SHLrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } +} + /// 'add' instruction - Simply turn this into an x86 reg,reg add instruction. void ISel::visitAdd(BinaryOperator &B) { @@ -157,13 +339,18 @@ void ISel::visitAdd(BinaryOperator &B) { case 4: // UInt, Int BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r); break; - case 8: // ULong, Long + // Here we have a pair of operands each occupying a pair of registers. + // We need to do an ADDrr32 of the least-significant pair immediately + // followed by an ADCrr32 (Add with Carry) of the most-significant pair. + // I don't know how we are representing these multi-register arguments. default: visitInstruction(B); // abort } } + + /// createSimpleX86InstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index d0d80e3226c..7e4f689fe2a 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -8,6 +8,7 @@ #include "X86InstrInfo.h" #include "llvm/Function.h" #include "llvm/iTerminators.h" +#include "llvm/iOther.h" #include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/Pass.h" @@ -55,6 +56,7 @@ namespace { // void visitReturnInst(ReturnInst &RI); void visitAdd(BinaryOperator &B); + void visitShiftInst(ShiftInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; @@ -141,6 +143,186 @@ void ISel::visitReturnInst(ReturnInst &I) { BuildMI(BB, X86::RET, 0); } +/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here +/// for constant immediate shift values, and for constant immediate +/// shift values equal to 1. Even the general case is sort of special, +/// because the shift amount has to be in CL, not just any old register. +/// +void +ISel::visitShiftInst (ShiftInst & I) +{ + unsigned Op0r = getReg (I.getOperand (0)); + unsigned DestReg = getReg (I); + unsigned operandSize = I.getOperand (0)->getType ()->getPrimitiveSize (); + bool isRightShift = (I.getOpcode () == Instruction::Shr); + bool isOperandUnsigned = I.getType ()->isUnsigned (); + bool isConstantShiftAmount = (isa (I.getOperand (1))); + if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) + { + // The shift amount is constant. Get its value. + uint64_t shAmt = CUI->getValue (); + // Emit: reg, shamt (shift-by-immediate opcode "ir" form.) + if (isRightShift) + { + if (isOperandUnsigned) + { + // This is a shift right logical (SHR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHRir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SHRir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SHRir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + else + { + // This is a shift right arithmetic (SAR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SARir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SARir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SARir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // This is a left shift (SHL). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHLir8, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 2: + BuildMI (BB, X86::SHLir16, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 4: + BuildMI (BB, X86::SHLir32, 2, + DestReg).addReg (Op0r).addZImm (shAmt); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // The shift amount is non-constant. + // + // In fact, you can only shift with a variable shift amount if + // that amount is already in the CL register, so we have to put it + // there first. + // + // Get it from the register it's in. + unsigned Op1r = getReg (I.getOperand (1)); + // Emit: move cl, shiftAmount (put the shift amount in CL.) + BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r); + // Emit: reg, cl (shift-by-CL opcode; "rr" form.) + if (isRightShift) + { + if (isOperandUnsigned) + { + // This is a shift right logical (SHR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHRrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SHRrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SHRrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + else + { + // This is a shift right arithmetic (SAR). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SARrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SARrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SARrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } + else + { + // This is a left shift (SHL). + switch (operandSize) + { + case 1: + BuildMI (BB, X86::SHLrr8, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 2: + BuildMI (BB, X86::SHLrr16, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 4: + BuildMI (BB, X86::SHLrr32, 2, + DestReg).addReg (Op0r).addReg (X86::CL); + break; + case 8: + default: + visitInstruction (I); + break; + } + } + } +} + /// 'add' instruction - Simply turn this into an x86 reg,reg add instruction. void ISel::visitAdd(BinaryOperator &B) { @@ -157,13 +339,18 @@ void ISel::visitAdd(BinaryOperator &B) { case 4: // UInt, Int BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r); break; - case 8: // ULong, Long + // Here we have a pair of operands each occupying a pair of registers. + // We need to do an ADDrr32 of the least-significant pair immediately + // followed by an ADCrr32 (Add with Carry) of the most-significant pair. + // I don't know how we are representing these multi-register arguments. default: visitInstruction(B); // abort } } + + /// createSimpleX86InstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def index 2388b9bf38d..519e7680d7e 100644 --- a/lib/Target/X86/X86InstrInfo.def +++ b/lib/Target/X86/X86InstrInfo.def @@ -37,15 +37,37 @@ I(NOOP , "nop", 0, X86II::Void) // nop 90 I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB // Move instructions -I(MOVir8 , "movb", 0, 0) // R = imm8 B0+ rb -I(MOVir16 , "movw", 0, 0) // R = imm16 B8+ rw -I(MOVir32 , "movl", 0, 0) // R = imm32 B8+ rd +I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r +I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r +I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r +I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb +I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw +I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd // Arithmetic instructions I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r I(ADDrr32 , "addl", 0, 0) // R32 += R32 02/r +// Shift instructions +I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4 +I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib +I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4 +I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib +I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4 +I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib +I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5 +I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib +I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5 +I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib +I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5 +I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib +I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7 +I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib +I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7 +I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib +I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7 +I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib // At this point, I is dead, so undefine the macro #undef I