diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 3adad780603..039982a5dd6 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -196,7 +196,7 @@ void LiveIntervals::updateSpilledInterval(Interval& li,
                                           VirtRegMap& vrm,
                                           int slot)
 {
-    assert(li.weight != std::numeric_limits<float>::infinity() &&
+    assert(li.weight != HUGE_VAL &&
            "attempt to spill already spilled interval!");
     Interval::Ranges oldRanges;
     swap(oldRanges, li.ranges);
@@ -253,7 +253,7 @@ void LiveIntervals::updateSpilledInterval(Interval& li,
         }
     }
     // the new spill weight is now infinity as it cannot be spilled again
-    li.weight = std::numeric_limits<float>::infinity();
+    li.weight = HUGE_VAL;
     DEBUG(std::cerr << '\n');
     DEBUG(std::cerr << "\t\t\t\tupdated interval: " << li << '\n');
 }
@@ -556,15 +556,13 @@ LiveIntervals::Interval& LiveIntervals::getOrCreateInterval(unsigned reg)
 
 LiveIntervals::Interval::Interval(unsigned r)
     : reg(r),
-      weight((MRegisterInfo::isPhysicalRegister(r) ?
-              std::numeric_limits<float>::infinity() : 0.0F))
+      weight((MRegisterInfo::isPhysicalRegister(r) ?  HUGE_VAL : 0.0F))
 {
-
 }
 
 bool LiveIntervals::Interval::spilled() const
 {
-    return (weight == std::numeric_limits<float>::infinity() &&
+    return (weight == HUGE_VAL &&
             MRegisterInfo::isVirtualRegister(reg));
 }
 
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 7759eec6386..dcfb597f954 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -351,7 +351,7 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
 
     DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
 
-    float minWeight = std::numeric_limits<float>::infinity();
+    float minWeight = HUGE_VAL;
     unsigned minReg = 0;
     const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
     for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);