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[TwoAddressInstructionPass] Try 3 Addr Conversion After Commuting.
TwoAddressInstructionPass stops after a successful commuting but 3 Addr conversion might be good for some cases. Consider: int foo(int a, int b) { return a + b; } Before this commit, we emit: addl %esi, %edi movl %edi, %eax ret After this commit, we try 3 Addr conversion: leal (%rsi,%rdi), %eax ret Patch by Volkan Keles <vkeles@apple.com>! Differential Revision: http://reviews.llvm.org/D10851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241206 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1207,12 +1207,24 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
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}
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}
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// If the instruction is convertible to 3 Addr, instead
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// of returning try 3 Addr transformation aggresively and
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// use this variable to check later. Because it might be better.
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// For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
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// instead of the following code.
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// addl %esi, %edi
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// movl %edi, %eax
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// ret
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bool commuted = false;
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// If it's profitable to commute, try to do so.
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if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
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commuted = true;
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++NumCommuted;
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if (AggressiveCommute)
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++NumAggrCommuted;
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return false;
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if (!MI.isConvertibleTo3Addr())
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return false;
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}
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if (shouldOnlyCommute)
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@ -1220,7 +1232,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
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// If there is one more use of regB later in the same MBB, consider
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// re-schedule this MI below it.
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if (EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
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if (!commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
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++NumReSchedDowns;
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return true;
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}
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@ -1237,6 +1249,10 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
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}
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}
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// Return if it is commuted but 3 addr conversion is failed.
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if (commuted)
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return false;
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// If there is one more use of regB later in the same MBB, consider
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// re-schedule it before this MI if it's legal.
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if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
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@ -39,7 +39,7 @@ define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8
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entry:
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; DARWIN-LABEL: t3:
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; DARWIN: shlq $32, %rcx
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; DARWIN-NEXT: orq %rcx, %rax
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; DARWIN-NEXT: leaq (%rax,%rcx), %rax
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; DARWIN-NEXT: shll $8
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; DARWIN-NOT: leaq
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%tmp21 = zext i32 %lb to i64
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@ -25,8 +25,7 @@ define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: leal
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; CHECK-NOT: leal
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; CHECK-NOT: mov
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; CHECK-NEXT: addl
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; CHECK-NEXT: addl
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; CHECK-NEXT: ret
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%add = add i32 %b, %a
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@ -7,8 +7,7 @@ define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind re
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entry:
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; CHECK: movl 48(%rsp), %eax
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; CHECK: addl 40(%rsp), %eax
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; LINUX: addl %r9d, %r8d
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; LINUX: movl %r8d, %eax
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; LINUX: leal (%r8,%r9), %eax
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%add = add nsw i32 %p6, %p5
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ret i32 %add
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}
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@ -27,10 +26,8 @@ entry:
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; on other platforms here (note the x86_64_sysvcc calling convention).
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define x86_64_sysvcc i32 @f8(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
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entry:
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; CHECK: addl %r9d, %r8d
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; CHECK: movl %r8d, %eax
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; LINUX: addl %r9d, %r8d
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; LINUX: movl %r8d, %eax
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; CHECK: leal (%r8,%r9), %eax
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; LINUX: leal (%r8,%r9), %eax
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%add = add nsw i32 %p6, %p5
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ret i32 %add
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}
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@ -23,7 +23,7 @@
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; X32: add
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; X32: add
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; X32: add
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; X32: add
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; X32: leal
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; X32: %for.body.3
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define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
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entry:
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