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Align i64 arguments to 64 bit boundaries.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-05-19 20:29:48 +00:00
parent c3b162857a
commit a1a7ba8382
2 changed files with 41 additions and 1 deletions
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8
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -975,9 +975,15 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
// argument which is not f32 or f64. // argument which is not f32 or f64.
bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
|| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
unsigned OrigAlign = ArgFlags.getOrigAlign();
bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Reg = State.AllocateReg(IntRegs, IntRegsSize); Reg = State.AllocateReg(IntRegs, IntRegsSize);
// If this is the first part of an i64 arg,
// the allocated register must be either A0 or A2.
if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
Reg = State.AllocateReg(IntRegs, IntRegsSize);
LocVT = MVT::i32; LocVT = MVT::i32;
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
// Allocate int register and shadow next int register. If first // Allocate int register and shadow next int register. If first
@ -1006,7 +1012,7 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
if (!Reg) { if (!Reg) {
unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes); unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
} else } else
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

34
test/CodeGen/Mips/i64arg.ll Normal file
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@ -0,0 +1,34 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:
; CHECK: addu $[[R1:[0-9]+]], $zero, $5
; CHECK: addu $[[R0:[0-9]+]], $zero, $4
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
; CHECK: lw $25, %call16(ff1)
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $[[R2:[0-9]+]], 96($sp)
; CHECK: lw $[[R3:[0-9]+]], 100($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: lw $25, %call16(ff2)
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
; CHECK: sw $[[R0]], 24($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: addu $6, $zero, $[[R2]]
; CHECK: addu $7, $zero, $[[R3]]
; CHECK: lw $25, %call16(ff3)
; CHECK: jalr $25
tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
ret void
}
declare void @ff1(i32, i64)
declare void @ff2(i64, double)
declare void @ff3(i32, i64, i32, i64)