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https://github.com/c64scene-ar/llvm-6502.git
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[ARM] Move the store combiner function down. NFC.
And flip its final condition. In preparation for a future patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
a31421e2dc
commit
a1aa4d3b36
@ -8648,147 +8648,6 @@ static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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/// PerformSTORECombine - Target-specific dag combine xforms for
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/// ISD::STORE.
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static SDValue PerformSTORECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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StoreSDNode *St = cast<StoreSDNode>(N);
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if (St->isVolatile())
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return SDValue();
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// Optimize trunc store (of multiple scalars) to shuffle and store. First,
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// pack all of the elements in one place. Next, store to memory in fewer
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// chunks.
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SDValue StVal = St->getValue();
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EVT VT = StVal.getValueType();
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if (St->isTruncatingStore() && VT.isVector()) {
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT StVT = St->getMemoryVT();
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unsigned NumElems = VT.getVectorNumElements();
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assert(StVT != VT && "Cannot truncate to the same type");
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unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
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unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
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// From, To sizes and ElemCount must be pow of two
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if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
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// We are going to use the original vector elt for storing.
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// Accumulated smaller vector elements must be a multiple of the store size.
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if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
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unsigned SizeRatio = FromEltSz / ToEltSz;
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assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
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// Create a type on which we perform the shuffle.
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EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
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NumElems*SizeRatio);
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assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
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SDLoc DL(St);
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SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
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SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
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for (unsigned i = 0; i < NumElems; ++i)
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ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
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// Can't shuffle using an illegal type.
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if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
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SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
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DAG.getUNDEF(WideVec.getValueType()),
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ShuffleVec.data());
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// At this point all of the data is stored at the bottom of the
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// register. We now need to save it to mem.
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// Find the largest store unit
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MVT StoreType = MVT::i8;
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for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
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tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
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MVT Tp = (MVT::SimpleValueType)tp;
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if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
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StoreType = Tp;
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}
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// Didn't find a legal store type.
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if (!TLI.isTypeLegal(StoreType))
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return SDValue();
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// Bitcast the original vector into a vector of store-size units
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EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
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StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
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assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
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SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
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SmallVector<SDValue, 8> Chains;
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SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
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TLI.getPointerTy());
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SDValue BasePtr = St->getBasePtr();
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// Perform one or more big stores into memory.
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unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
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for (unsigned I = 0; I < E; I++) {
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SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
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StoreType, ShuffWide,
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DAG.getIntPtrConstant(I));
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SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
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St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment());
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BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
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Increment);
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Chains.push_back(Ch);
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}
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
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}
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if (!ISD::isNormalStore(St))
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return SDValue();
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// Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
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// ARM stores of arguments in the same cache line.
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if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
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StVal.getNode()->hasOneUse()) {
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SelectionDAG &DAG = DCI.DAG;
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bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
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SDLoc DL(St);
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SDValue BasePtr = St->getBasePtr();
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SDValue NewST1 = DAG.getStore(St->getChain(), DL,
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StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
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BasePtr, St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment());
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SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
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DAG.getConstant(4, MVT::i32));
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return DAG.getStore(NewST1.getValue(0), DL,
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StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
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OffsetPtr, St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(),
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std::min(4U, St->getAlignment() / 2));
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}
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if (StVal.getValueType() != MVT::i64 ||
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StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return SDValue();
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// Bitcast an i64 store extracted from a vector to f64.
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// Otherwise, the i64 value will be legalized to a pair of i32 values.
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SelectionDAG &DAG = DCI.DAG;
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SDLoc dl(StVal);
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SDValue IntVec = StVal.getOperand(0);
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EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
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IntVec.getValueType().getVectorNumElements());
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SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
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SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
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Vec, StVal.getOperand(1));
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dl = SDLoc(N);
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SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
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// Make the DAGCombiner fold the bitcasts.
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DCI.AddToWorklist(Vec.getNode());
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DCI.AddToWorklist(ExtElt.getNode());
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DCI.AddToWorklist(V.getNode());
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return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
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St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment(),
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St->getAAInfo());
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}
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/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
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/// are normal, non-volatile loads. If so, it is profitable to bitcast an
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/// i64 vector to have f64 elements, since the value can then be loaded
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@ -9253,6 +9112,149 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
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return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
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}
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/// PerformSTORECombine - Target-specific dag combine xforms for
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/// ISD::STORE.
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static SDValue PerformSTORECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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StoreSDNode *St = cast<StoreSDNode>(N);
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if (St->isVolatile())
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return SDValue();
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// Optimize trunc store (of multiple scalars) to shuffle and store. First,
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// pack all of the elements in one place. Next, store to memory in fewer
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// chunks.
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SDValue StVal = St->getValue();
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EVT VT = StVal.getValueType();
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if (St->isTruncatingStore() && VT.isVector()) {
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SelectionDAG &DAG = DCI.DAG;
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT StVT = St->getMemoryVT();
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unsigned NumElems = VT.getVectorNumElements();
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assert(StVT != VT && "Cannot truncate to the same type");
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unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
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unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
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// From, To sizes and ElemCount must be pow of two
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if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
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// We are going to use the original vector elt for storing.
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// Accumulated smaller vector elements must be a multiple of the store size.
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if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
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unsigned SizeRatio = FromEltSz / ToEltSz;
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assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
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// Create a type on which we perform the shuffle.
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EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
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NumElems*SizeRatio);
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assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
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SDLoc DL(St);
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SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
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SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
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for (unsigned i = 0; i < NumElems; ++i)
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ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
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// Can't shuffle using an illegal type.
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if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
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SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
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DAG.getUNDEF(WideVec.getValueType()),
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ShuffleVec.data());
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// At this point all of the data is stored at the bottom of the
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// register. We now need to save it to mem.
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// Find the largest store unit
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MVT StoreType = MVT::i8;
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for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
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tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
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MVT Tp = (MVT::SimpleValueType)tp;
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if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
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StoreType = Tp;
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}
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// Didn't find a legal store type.
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if (!TLI.isTypeLegal(StoreType))
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return SDValue();
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// Bitcast the original vector into a vector of store-size units
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EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
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StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
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assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
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SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
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SmallVector<SDValue, 8> Chains;
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SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
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TLI.getPointerTy());
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SDValue BasePtr = St->getBasePtr();
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// Perform one or more big stores into memory.
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unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
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for (unsigned I = 0; I < E; I++) {
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SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
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StoreType, ShuffWide,
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DAG.getIntPtrConstant(I));
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SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
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St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment());
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BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
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Increment);
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Chains.push_back(Ch);
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}
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
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}
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if (!ISD::isNormalStore(St))
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return SDValue();
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// Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
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// ARM stores of arguments in the same cache line.
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if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
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StVal.getNode()->hasOneUse()) {
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SelectionDAG &DAG = DCI.DAG;
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bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
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SDLoc DL(St);
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SDValue BasePtr = St->getBasePtr();
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SDValue NewST1 = DAG.getStore(St->getChain(), DL,
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StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
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BasePtr, St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment());
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SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
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DAG.getConstant(4, MVT::i32));
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return DAG.getStore(NewST1.getValue(0), DL,
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StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
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OffsetPtr, St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(),
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std::min(4U, St->getAlignment() / 2));
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}
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if (StVal.getValueType() == MVT::i64 &&
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StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
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// Bitcast an i64 store extracted from a vector to f64.
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// Otherwise, the i64 value will be legalized to a pair of i32 values.
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SelectionDAG &DAG = DCI.DAG;
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SDLoc dl(StVal);
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SDValue IntVec = StVal.getOperand(0);
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EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
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IntVec.getValueType().getVectorNumElements());
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SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
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SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
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Vec, StVal.getOperand(1));
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dl = SDLoc(N);
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SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
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// Make the DAGCombiner fold the bitcasts.
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DCI.AddToWorklist(Vec.getNode());
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DCI.AddToWorklist(ExtElt.getNode());
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DCI.AddToWorklist(V.getNode());
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return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
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St->getPointerInfo(), St->isVolatile(),
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St->isNonTemporal(), St->getAlignment(),
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St->getAAInfo());
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}
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return SDValue();
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}
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// isConstVecPow2 - Return true if each vector element is a power of 2, all
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// elements are the same constant, C, and Log2(C) ranges from 1 to 32.
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static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
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