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https://github.com/c64scene-ar/llvm-6502.git
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Completely reject instructions that have an operand in their
ins/outs list that isn't specified by their asmstring. Previously the asmmatcher would just force a 0 register into it, which clearly isn't right. Mark a bunch of ARM instructions that use this as isCodeGenOnly. Some of them are clearly pseudo instructions (like t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will either need to be removed or the asmmatcher will need to be taught about it (someday). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
e6c6cec82b
commit
a1ca91af4e
@ -1352,39 +1352,41 @@ let isBranch = 1, isTerminator = 1 in {
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def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
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"b\t$target", [(br bb:$target)]>;
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "mov\tpc, $target$jt",
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
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let Inst{11-4} = 0b00000000;
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let Inst{15-12} = 0b1111;
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = 0b1101;
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let Inst{27-25} = 0b000;
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}
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def BR_JTm : JTI<(outs),
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(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "ldr\tpc, $target$jt",
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]> {
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let Inst{15-12} = 0b1111;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-25} = 0b011;
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}
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def BR_JTadd : JTI<(outs),
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(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "add\tpc, $target, $idx$jt",
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[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
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imm:$id)]> {
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let Inst{15-12} = 0b1111;
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let Inst{20} = 0; // S bit
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let Inst{24-21} = 0b0100;
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let Inst{27-25} = 0b000;
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}
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} // isNotDuplicable = 1, isIndirectBranch = 1
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let isNotDuplicable = 1, isIndirectBranch = 1,
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// FIXME: $imm field is not specified by asm string. Mark as cgonly.
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isCodeGenOnly = 1 in {
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def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "mov\tpc, $target$jt",
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
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let Inst{11-4} = 0b00000000;
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let Inst{15-12} = 0b1111;
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = 0b1101;
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let Inst{27-25} = 0b000;
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}
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def BR_JTm : JTI<(outs),
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(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "ldr\tpc, $target$jt",
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]> {
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let Inst{15-12} = 0b1111;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-25} = 0b011;
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}
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def BR_JTadd : JTI<(outs),
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(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "add\tpc, $target, $idx$jt",
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[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
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imm:$id)]> {
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let Inst{15-12} = 0b1111;
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let Inst{20} = 0; // S bit
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let Inst{24-21} = 0b0100;
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let Inst{27-25} = 0b000;
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}
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} // isNotDuplicable = 1, isIndirectBranch = 1
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} // isBarrier = 1
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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@ -1494,7 +1496,8 @@ def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
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// Load doubleword
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def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
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@ -1595,7 +1598,8 @@ def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
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[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
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// Store doubleword
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
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def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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StMiscFrm, IIC_iStore_d_r,
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"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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@ -931,7 +931,8 @@ defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in { // $dst doesn't exist in asmstring?
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// Load doubleword
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def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
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(ins t2addrmode_imm8s4:$addr),
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@ -1078,7 +1079,8 @@ defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
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def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
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(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
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IIC_iStore_d_r, "strd", "\t$src1, $addr", []>;
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@ -1195,6 +1197,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
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let Inst{11-8} = 0b1100;
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}
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let isCodeGenOnly = 1 in // $base doesn't exist in asmstring?
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def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
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"\t[pc, $imm]", []> {
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let Inst{31-25} = 0b1111100;
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@ -2457,7 +2460,8 @@ def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
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let Inst{12} = 1;
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}
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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let isNotDuplicable = 1, isIndirectBranch = 1,
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isCodeGenOnly = 1 in { // $id doesn't exist in asmstring, should be lowered.
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def t2BR_JT :
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T2JTI<(outs),
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(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
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@ -2472,6 +2476,7 @@ def t2BR_JT :
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}
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// FIXME: Add a non-pc based case that can be predicated.
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let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
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def t2TBB :
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T2JTI<(outs),
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(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
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@ -2483,6 +2488,7 @@ def t2TBB :
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let Inst{7-4} = 0b0000; // B form
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}
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let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
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def t2TBH :
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T2JTI<(outs),
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(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
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@ -1176,27 +1176,21 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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continue;
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}
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// Otherwise, this must be a tied operand if not, it is something that is
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// mentioned in the ins/outs list but not in the asm string.
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int TiedOp = OpInfo.getTiedRegister();
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if (TiedOp == -1)
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throw TGError(II.TheDef->getLoc(), "Instruction '" +
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II.TheDef->getName() + "' has operand '" + OpInfo.Name +
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"' that doesn't appear in asm string!");
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// If this operand is tied to a previous one, just copy the MCInst operand
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// from the earlier one.
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int TiedOp = OpInfo.getTiedRegister();
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if (TiedOp != -1) {
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// Copy the tied operand. We can only tie single MCOperand values.
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assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
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assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!");
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CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
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Signature += "__Tie" + itostr(TiedOp);
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continue;
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}
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// Otherwise this is some sort of dummy operand that is mentioned in the
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// ins/outs list but not mentioned in the asmstring, brutalize a dummy
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// value into the operand.
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// FIXME: This is a terrible hack: If an MCInst operand doesn't occur in
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// the asmstring, there is no way to parse something meaningful.
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// Just assume it is a zero register for now.
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CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
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Signature += "__Imp";
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// Copy the tied operand. We can only tie single MCOperand values.
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assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
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assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!");
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CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
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Signature += "__Tie" + itostr(TiedOp);
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}
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II.ConversionFnKind = Signature;
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