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Completely reject instructions that have an operand in their

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ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-11-02 23:40:41 +00:00
parent e6c6cec82b
commit a1ca91af4e
3 changed files with 60 additions and 56 deletions
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10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1352,7 +1352,9 @@ let isBranch = 1, isTerminator = 1 in {
def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
"b\t$target", [(br bb:$target)]>;
let isNotDuplicable = 1, isIndirectBranch = 1 in {
let isNotDuplicable = 1, isIndirectBranch = 1,
// FIXME: $imm field is not specified by asm string. Mark as cgonly.
isCodeGenOnly = 1 in {
def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
IIC_Br, "mov\tpc, $target$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
@ -1494,7 +1496,8 @@ def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
// Load doubleword
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
@ -1595,7 +1598,8 @@ def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
// Store doubleword
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
StMiscFrm, IIC_iStore_d_r,
"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;

12
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -931,7 +931,8 @@ defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
UnOpFrag<(sextloadi8 node:$Src)>>;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
isCodeGenOnly = 1 in { // $dst doesn't exist in asmstring?
// Load doubleword
def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
(ins t2addrmode_imm8s4:$addr),
@ -1078,7 +1079,8 @@ defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
// Store doubleword
let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
IIC_iStore_d_r, "strd", "\t$src1, $addr", []>;
@ -1195,6 +1197,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> {
let Inst{11-8} = 0b1100;
}
let isCodeGenOnly = 1 in // $base doesn't exist in asmstring?
def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoad_i, opc,
"\t[pc, $imm]", []> {
let Inst{31-25} = 0b1111100;
@ -2457,7 +2460,8 @@ def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
let Inst{12} = 1;
}
let isNotDuplicable = 1, isIndirectBranch = 1 in {
let isNotDuplicable = 1, isIndirectBranch = 1,
isCodeGenOnly = 1 in { // $id doesn't exist in asmstring, should be lowered.
def t2BR_JT :
T2JTI<(outs),
(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
@ -2472,6 +2476,7 @@ def t2BR_JT :
}
// FIXME: Add a non-pc based case that can be predicated.
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
def t2TBB :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
@ -2483,6 +2488,7 @@ def t2TBB :
let Inst{7-4} = 0b0000; // B form
}
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
def t2TBH :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),

20
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -1176,27 +1176,21 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
continue;
}
// Otherwise, this must be a tied operand if not, it is something that is
// mentioned in the ins/outs list but not in the asm string.
int TiedOp = OpInfo.getTiedRegister();
if (TiedOp == -1)
throw TGError(II.TheDef->getLoc(), "Instruction '" +
II.TheDef->getName() + "' has operand '" + OpInfo.Name +
"' that doesn't appear in asm string!");
// If this operand is tied to a previous one, just copy the MCInst operand
// from the earlier one.
int TiedOp = OpInfo.getTiedRegister();
if (TiedOp != -1) {
// Copy the tied operand. We can only tie single MCOperand values.
assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
assert(i > unsigned(TiedOp) && "Tied operand preceeds its target!");
CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n";
Signature += "__Tie" + itostr(TiedOp);
continue;
}
// Otherwise this is some sort of dummy operand that is mentioned in the
// ins/outs list but not mentioned in the asmstring, brutalize a dummy
// value into the operand.
// FIXME: This is a terrible hack: If an MCInst operand doesn't occur in
// the asmstring, there is no way to parse something meaningful.
// Just assume it is a zero register for now.
CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
Signature += "__Imp";
}
II.ConversionFnKind = Signature;