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Machine-independent code generation routines used in instruction
selection. These used to live in several different places before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@719 91177308-0d34-0410-b5e6-96231b3b80d8
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102
include/llvm/CodeGen/InstrSelectionSupport.h
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102
include/llvm/CodeGen/InstrSelectionSupport.h
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@ -0,0 +1,102 @@
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// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// InstrSelectionSupport.h
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//
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// Purpose:
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// Target-independent instruction selection code.
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// See SparcInstrSelection.cpp for usage.
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//
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// History:
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// 10/10/01 - Vikram Adve - Created
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//**************************************************************************/
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#ifndef LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H
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#define LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H
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#include "llvm/Instruction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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class Method;
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class InstrForest;
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class MachineInstr;
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class InstructionNode;
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class TmpInstruction;
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class ConstPoolVal;
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class TargetMachine;
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//************************ Exported Functions ******************************/
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//---------------------------------------------------------------------------
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// Function: FoldGetElemChain
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//
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// Purpose:
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// Fold a chain of GetElementPtr instructions into an equivalent
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// (Pointer, IndexVector) pair. Returns the pointer Value, and
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// stores the resulting IndexVector in argument chainIdxVec.
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//---------------------------------------------------------------------------
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Value* FoldGetElemChain (const InstructionNode* getElemInstrNode,
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vector<ConstPoolVal*>& chainIdxVec);
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// Purpose:
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated
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// "0" register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void Set2OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int resultPosition = 1);
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void Set3OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int op2Position = 1,
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int resultPosition = 2);
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//---------------------------------------------------------------------------
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// Function: ChooseRegOrImmed
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//
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// Purpose:
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//
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//---------------------------------------------------------------------------
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MachineOperand::MachineOperandType
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ChooseRegOrImmed (Value* val,
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MachineOpCode opCode,
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const TargetMachine& targetMachine,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue);
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//**************************************************************************/
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#endif
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357
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
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357
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
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// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// InstrSelectionSupport.h
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//
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// Purpose:
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// Target-independent instruction selection code.
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// See SparcInstrSelection.cpp for usage.
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//
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// History:
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// 10/10/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/ConstPoolVals.h"
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#include "llvm/Instruction.h"
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#include "llvm/Type.h"
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#include "llvm/iMemory.h"
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//*************************** Local Functions ******************************/
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inline int64_t
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GetSignedIntConstantValue(Value* val, bool& isValidConstant)
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{
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int64_t intValue = 0;
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isValidConstant = false;
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if (val->getValueType() == Value::ConstantVal)
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{
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switch(val->getType()->getPrimitiveID())
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{
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case Type::BoolTyID:
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intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
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isValidConstant = true;
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break;
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case Type::SByteTyID:
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case Type::ShortTyID:
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case Type::IntTyID:
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case Type::LongTyID:
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intValue = ((ConstPoolSInt*) val)->getValue();
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isValidConstant = true;
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break;
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default:
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break;
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}
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}
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return intValue;
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}
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inline uint64_t
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GetUnsignedIntConstantValue(Value* val, bool& isValidConstant)
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{
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uint64_t intValue = 0;
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isValidConstant = false;
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if (val->getValueType() == Value::ConstantVal)
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{
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switch(val->getType()->getPrimitiveID())
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{
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case Type::BoolTyID:
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intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
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isValidConstant = true;
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break;
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case Type::UByteTyID:
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case Type::UShortTyID:
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case Type::UIntTyID:
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case Type::ULongTyID:
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intValue = ((ConstPoolUInt*) val)->getValue();
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isValidConstant = true;
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break;
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default:
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break;
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}
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}
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return intValue;
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}
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inline int64_t
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GetConstantValueAsSignedInt(Value* val, bool& isValidConstant)
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{
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int64_t intValue = 0;
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if (val->getType()->isSigned())
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{
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intValue = GetSignedIntConstantValue(val, isValidConstant);
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}
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else // non-numeric types will fall here
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{
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uint64_t uintValue = GetUnsignedIntConstantValue(val, isValidConstant);
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if (isValidConstant && uintValue < INT64_MAX) // safe to use signed
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intValue = (int64_t) uintValue;
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else
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isValidConstant = false;
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}
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return intValue;
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}
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//---------------------------------------------------------------------------
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// Function: FoldGetElemChain
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//
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// Purpose:
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// Fold a chain of GetElementPtr instructions into an equivalent
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// (Pointer, IndexVector) pair. Returns the pointer Value, and
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// stores the resulting IndexVector in argument chainIdxVec.
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//---------------------------------------------------------------------------
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Value*
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FoldGetElemChain(const InstructionNode* getElemInstrNode,
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vector<ConstPoolVal*>& chainIdxVec)
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{
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MemAccessInst* getElemInst = (MemAccessInst*)
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getElemInstrNode->getInstruction();
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// Initialize return values from the incoming instruction
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Value* ptrVal = getElemInst->getPtrOperand();
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chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
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// Now chase the chain of getElementInstr instructions, if any
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InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
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while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
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ptrChild->getOpLabel() == GetElemPtrIdx)
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{
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// Child is a GetElemPtr instruction
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getElemInst = (MemAccessInst*)
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((InstructionNode*) ptrChild)->getInstruction();
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const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
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// Get the pointer value out of ptrChild and *prepend* its index vector
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ptrVal = getElemInst->getPtrOperand();
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chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
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ptrChild = ptrChild->leftChild();
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}
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return ptrVal;
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}
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated "0"
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// register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void
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Set2OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int resultPosition)
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{
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Set3OperandsFromInstr(minstr, vmInstrNode, target,
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canDiscardResult, op1Position,
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/*op2Position*/ -1, resultPosition);
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}
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#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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unsigned
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Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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int resultPosition)
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{
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assert(op1Position >= 0);
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assert(resultPosition >= 0);
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unsigned returnFlags = 0x0;
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// Check if operand 1 is 0. If so, try to use a hardwired 0 register.
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Value* op1Value = vmInstrNode->leftChild()->getValue();
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bool isValidConstant;
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int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
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if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
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else
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{
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if (isa<ConstPoolVal>(op1Value))
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{
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// value is constant and must be loaded from constant pool
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returnFlags = returnFlags | (1 << op1Position);
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}
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minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
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op1Value);
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}
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// Check if operand 2 (if any) fits in the immed. field of the instruction,
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// or if it is 0 and can use a dedicated machine register
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if (op2Position >= 0)
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{
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Value* op2Value = vmInstrNode->rightChild()->getValue();
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int64_t immedValue;
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unsigned int machineRegNum;
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MachineOperand::MachineOperandType
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op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
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/*canUseImmed*/ true,
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machineRegNum, immedValue);
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if (op2type == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperand(op2Position, machineRegNum);
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else if (op2type == MachineOperand::MO_VirtualRegister)
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{
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if (isa<ConstPoolVal>(op2Value))
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{
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// value is constant and must be loaded from constant pool
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returnFlags = returnFlags | (1 << op2Position);
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}
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minstr->SetMachineOperand(op2Position, op2type, op2Value);
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}
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else
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{
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assert(op2type != MO_CCRegister);
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minstr->SetMachineOperand(op2Position, op2type, immedValue);
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}
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}
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// If operand 3 (result) can be discarded, use a dead register if one exists
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if (canDiscardResult && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
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else
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minstr->SetMachineOperand(resultPosition,
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MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
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return returnFlags;
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}
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#endif
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void
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Set3OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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int resultPosition)
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{
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assert(op1Position >= 0);
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assert(resultPosition >= 0);
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// operand 1
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minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->leftChild()->getValue());
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// operand 2 (if any)
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if (op2Position >= 0)
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minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
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vmInstrNode->rightChild()->getValue());
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// result operand: if it can be discarded, use a dead register if one exists
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if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
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minstr->SetMachineOperand(resultPosition,
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target.getRegInfo().getZeroRegNum());
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else
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minstr->SetMachineOperand(resultPosition,
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MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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// Check for the common case first: argument is not constant
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//
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ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
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if (!CPV) return opType;
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if (CPV->getType() == Type::BoolTy)
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{
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ConstPoolBool *CPB = (ConstPoolBool*)CPV;
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if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
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{
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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return MachineOperand::MO_MachineRegister;
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}
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getImmedValue = 1;
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return MachineOperand::MO_SignExtendedImmed;
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}
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if (!CPV->getType()->isIntegral()) return opType;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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// unsigned constants to signed).
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//
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int64_t intValue;
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if (CPV->getType()->isSigned())
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{
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intValue = ((ConstPoolSInt*)CPV)->getValue();
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}
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else
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{
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uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
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if (V >= INT64_MAX) return opType;
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intValue = (int64_t)V;
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}
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if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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else if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = MachineOperand::MO_SignExtendedImmed;
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getImmedValue = intValue;
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}
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return opType;
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}
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|
357
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
Normal file
357
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
Normal file
@ -0,0 +1,357 @@
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// $Id$ -*-c++-*-
|
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//***************************************************************************
|
||||
// File:
|
||||
// InstrSelectionSupport.h
|
||||
//
|
||||
// Purpose:
|
||||
// Target-independent instruction selection code.
|
||||
// See SparcInstrSelection.cpp for usage.
|
||||
//
|
||||
// History:
|
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// 10/10/01 - Vikram Adve - Created
|
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//**************************************************************************/
|
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|
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/ConstPoolVals.h"
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#include "llvm/Instruction.h"
|
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#include "llvm/Type.h"
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#include "llvm/iMemory.h"
|
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|
||||
|
||||
//*************************** Local Functions ******************************/
|
||||
|
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inline int64_t
|
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GetSignedIntConstantValue(Value* val, bool& isValidConstant)
|
||||
{
|
||||
int64_t intValue = 0;
|
||||
isValidConstant = false;
|
||||
|
||||
if (val->getValueType() == Value::ConstantVal)
|
||||
{
|
||||
switch(val->getType()->getPrimitiveID())
|
||||
{
|
||||
case Type::BoolTyID:
|
||||
intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
|
||||
isValidConstant = true;
|
||||
break;
|
||||
case Type::SByteTyID:
|
||||
case Type::ShortTyID:
|
||||
case Type::IntTyID:
|
||||
case Type::LongTyID:
|
||||
intValue = ((ConstPoolSInt*) val)->getValue();
|
||||
isValidConstant = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return intValue;
|
||||
}
|
||||
|
||||
inline uint64_t
|
||||
GetUnsignedIntConstantValue(Value* val, bool& isValidConstant)
|
||||
{
|
||||
uint64_t intValue = 0;
|
||||
isValidConstant = false;
|
||||
|
||||
if (val->getValueType() == Value::ConstantVal)
|
||||
{
|
||||
switch(val->getType()->getPrimitiveID())
|
||||
{
|
||||
case Type::BoolTyID:
|
||||
intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
|
||||
isValidConstant = true;
|
||||
break;
|
||||
case Type::UByteTyID:
|
||||
case Type::UShortTyID:
|
||||
case Type::UIntTyID:
|
||||
case Type::ULongTyID:
|
||||
intValue = ((ConstPoolUInt*) val)->getValue();
|
||||
isValidConstant = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return intValue;
|
||||
}
|
||||
|
||||
|
||||
inline int64_t
|
||||
GetConstantValueAsSignedInt(Value* val, bool& isValidConstant)
|
||||
{
|
||||
int64_t intValue = 0;
|
||||
|
||||
if (val->getType()->isSigned())
|
||||
{
|
||||
intValue = GetSignedIntConstantValue(val, isValidConstant);
|
||||
}
|
||||
else // non-numeric types will fall here
|
||||
{
|
||||
uint64_t uintValue = GetUnsignedIntConstantValue(val, isValidConstant);
|
||||
if (isValidConstant && uintValue < INT64_MAX) // safe to use signed
|
||||
intValue = (int64_t) uintValue;
|
||||
else
|
||||
isValidConstant = false;
|
||||
}
|
||||
|
||||
return intValue;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Function: FoldGetElemChain
|
||||
//
|
||||
// Purpose:
|
||||
// Fold a chain of GetElementPtr instructions into an equivalent
|
||||
// (Pointer, IndexVector) pair. Returns the pointer Value, and
|
||||
// stores the resulting IndexVector in argument chainIdxVec.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
Value*
|
||||
FoldGetElemChain(const InstructionNode* getElemInstrNode,
|
||||
vector<ConstPoolVal*>& chainIdxVec)
|
||||
{
|
||||
MemAccessInst* getElemInst = (MemAccessInst*)
|
||||
getElemInstrNode->getInstruction();
|
||||
|
||||
// Initialize return values from the incoming instruction
|
||||
Value* ptrVal = getElemInst->getPtrOperand();
|
||||
chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
|
||||
|
||||
// Now chase the chain of getElementInstr instructions, if any
|
||||
InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
|
||||
while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
|
||||
ptrChild->getOpLabel() == GetElemPtrIdx)
|
||||
{
|
||||
// Child is a GetElemPtr instruction
|
||||
getElemInst = (MemAccessInst*)
|
||||
((InstructionNode*) ptrChild)->getInstruction();
|
||||
const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
|
||||
|
||||
// Get the pointer value out of ptrChild and *prepend* its index vector
|
||||
ptrVal = getElemInst->getPtrOperand();
|
||||
chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
|
||||
|
||||
ptrChild = ptrChild->leftChild();
|
||||
}
|
||||
|
||||
return ptrVal;
|
||||
}
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Function Set2OperandsFromInstr
|
||||
// Function Set3OperandsFromInstr
|
||||
//
|
||||
// For the common case of 2- and 3-operand arithmetic/logical instructions,
|
||||
// set the m/c instr. operands directly from the VM instruction's operands.
|
||||
// Check whether the first or second operand is 0 and can use a dedicated "0"
|
||||
// register.
|
||||
// Check whether the second operand should use an immediate field or register.
|
||||
// (First and third operands are never immediates for such instructions.)
|
||||
//
|
||||
// Arguments:
|
||||
// canDiscardResult: Specifies that the result operand can be discarded
|
||||
// by using the dedicated "0"
|
||||
//
|
||||
// op1position, op2position and resultPosition: Specify in which position
|
||||
// in the machine instruction the 3 operands (arg1, arg2
|
||||
// and result) should go.
|
||||
//
|
||||
// RETURN VALUE: unsigned int flags, where
|
||||
// flags & 0x01 => operand 1 is constant and needs a register
|
||||
// flags & 0x02 => operand 2 is constant and needs a register
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
void
|
||||
Set2OperandsFromInstr(MachineInstr* minstr,
|
||||
InstructionNode* vmInstrNode,
|
||||
const TargetMachine& target,
|
||||
bool canDiscardResult,
|
||||
int op1Position,
|
||||
int resultPosition)
|
||||
{
|
||||
Set3OperandsFromInstr(minstr, vmInstrNode, target,
|
||||
canDiscardResult, op1Position,
|
||||
/*op2Position*/ -1, resultPosition);
|
||||
}
|
||||
|
||||
#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
|
||||
#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
|
||||
unsigned
|
||||
Set3OperandsFromInstrJUNK(MachineInstr* minstr,
|
||||
InstructionNode* vmInstrNode,
|
||||
const TargetMachine& target,
|
||||
bool canDiscardResult,
|
||||
int op1Position,
|
||||
int op2Position,
|
||||
int resultPosition)
|
||||
{
|
||||
assert(op1Position >= 0);
|
||||
assert(resultPosition >= 0);
|
||||
|
||||
unsigned returnFlags = 0x0;
|
||||
|
||||
// Check if operand 1 is 0. If so, try to use a hardwired 0 register.
|
||||
Value* op1Value = vmInstrNode->leftChild()->getValue();
|
||||
bool isValidConstant;
|
||||
int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
|
||||
if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
|
||||
minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
|
||||
else
|
||||
{
|
||||
if (isa<ConstPoolVal>(op1Value))
|
||||
{
|
||||
// value is constant and must be loaded from constant pool
|
||||
returnFlags = returnFlags | (1 << op1Position);
|
||||
}
|
||||
minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
|
||||
op1Value);
|
||||
}
|
||||
|
||||
// Check if operand 2 (if any) fits in the immed. field of the instruction,
|
||||
// or if it is 0 and can use a dedicated machine register
|
||||
if (op2Position >= 0)
|
||||
{
|
||||
Value* op2Value = vmInstrNode->rightChild()->getValue();
|
||||
int64_t immedValue;
|
||||
unsigned int machineRegNum;
|
||||
|
||||
MachineOperand::MachineOperandType
|
||||
op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
|
||||
/*canUseImmed*/ true,
|
||||
machineRegNum, immedValue);
|
||||
|
||||
if (op2type == MachineOperand::MO_MachineRegister)
|
||||
minstr->SetMachineOperand(op2Position, machineRegNum);
|
||||
else if (op2type == MachineOperand::MO_VirtualRegister)
|
||||
{
|
||||
if (isa<ConstPoolVal>(op2Value))
|
||||
{
|
||||
// value is constant and must be loaded from constant pool
|
||||
returnFlags = returnFlags | (1 << op2Position);
|
||||
}
|
||||
minstr->SetMachineOperand(op2Position, op2type, op2Value);
|
||||
}
|
||||
else
|
||||
{
|
||||
assert(op2type != MO_CCRegister);
|
||||
minstr->SetMachineOperand(op2Position, op2type, immedValue);
|
||||
}
|
||||
}
|
||||
|
||||
// If operand 3 (result) can be discarded, use a dead register if one exists
|
||||
if (canDiscardResult && target.zeroRegNum >= 0)
|
||||
minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
|
||||
else
|
||||
minstr->SetMachineOperand(resultPosition,
|
||||
MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
|
||||
|
||||
return returnFlags;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
Set3OperandsFromInstr(MachineInstr* minstr,
|
||||
InstructionNode* vmInstrNode,
|
||||
const TargetMachine& target,
|
||||
bool canDiscardResult,
|
||||
int op1Position,
|
||||
int op2Position,
|
||||
int resultPosition)
|
||||
{
|
||||
assert(op1Position >= 0);
|
||||
assert(resultPosition >= 0);
|
||||
|
||||
// operand 1
|
||||
minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
|
||||
vmInstrNode->leftChild()->getValue());
|
||||
|
||||
// operand 2 (if any)
|
||||
if (op2Position >= 0)
|
||||
minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
|
||||
vmInstrNode->rightChild()->getValue());
|
||||
|
||||
// result operand: if it can be discarded, use a dead register if one exists
|
||||
if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
|
||||
minstr->SetMachineOperand(resultPosition,
|
||||
target.getRegInfo().getZeroRegNum());
|
||||
else
|
||||
minstr->SetMachineOperand(resultPosition,
|
||||
MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
|
||||
}
|
||||
|
||||
|
||||
MachineOperand::MachineOperandType
|
||||
ChooseRegOrImmed(Value* val,
|
||||
MachineOpCode opCode,
|
||||
const TargetMachine& target,
|
||||
bool canUseImmed,
|
||||
unsigned int& getMachineRegNum,
|
||||
int64_t& getImmedValue)
|
||||
{
|
||||
MachineOperand::MachineOperandType opType =
|
||||
MachineOperand::MO_VirtualRegister;
|
||||
getMachineRegNum = 0;
|
||||
getImmedValue = 0;
|
||||
|
||||
// Check for the common case first: argument is not constant
|
||||
//
|
||||
ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
|
||||
if (!CPV) return opType;
|
||||
|
||||
if (CPV->getType() == Type::BoolTy)
|
||||
{
|
||||
ConstPoolBool *CPB = (ConstPoolBool*)CPV;
|
||||
if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
|
||||
{
|
||||
getMachineRegNum = target.getRegInfo().getZeroRegNum();
|
||||
return MachineOperand::MO_MachineRegister;
|
||||
}
|
||||
|
||||
getImmedValue = 1;
|
||||
return MachineOperand::MO_SignExtendedImmed;
|
||||
}
|
||||
|
||||
if (!CPV->getType()->isIntegral()) return opType;
|
||||
|
||||
// Now get the constant value and check if it fits in the IMMED field.
|
||||
// Take advantage of the fact that the max unsigned value will rarely
|
||||
// fit into any IMMED field and ignore that case (i.e., cast smaller
|
||||
// unsigned constants to signed).
|
||||
//
|
||||
int64_t intValue;
|
||||
if (CPV->getType()->isSigned())
|
||||
{
|
||||
intValue = ((ConstPoolSInt*)CPV)->getValue();
|
||||
}
|
||||
else
|
||||
{
|
||||
uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
|
||||
if (V >= INT64_MAX) return opType;
|
||||
intValue = (int64_t)V;
|
||||
}
|
||||
|
||||
if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
|
||||
{
|
||||
opType = MachineOperand::MO_MachineRegister;
|
||||
getMachineRegNum = target.getRegInfo().getZeroRegNum();
|
||||
}
|
||||
else if (canUseImmed &&
|
||||
target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
|
||||
{
|
||||
opType = MachineOperand::MO_SignExtendedImmed;
|
||||
getImmedValue = intValue;
|
||||
}
|
||||
|
||||
return opType;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user