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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204476 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
1f1c0495d0
commit
a1d28f6dd7
lib/Target/R600
test/CodeGen/R600
@ -165,6 +165,9 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
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addPass(createR600VectorRegMerger(*TM));
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} else {
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addPass(createSIFixSGPRCopiesPass(*TM));
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// SIFixSGPRCopies can generate a lot of duplicate instructions,
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// so we need to run MachineCSE afterwards.
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addPass(&MachineCSEID);
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}
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return false;
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}
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@ -25,8 +25,6 @@
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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@ -407,7 +405,7 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
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.addImm(0);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
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.addImm(RSRC_DATA_FORMAT >> 32);
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.addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
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.addReg(SubRegHiLo)
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.addImm(AMDGPU::sub0)
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@ -369,6 +369,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let EXP_CNT = 1;
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let neverHasSideEffects = 1;
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let UseNamedOperandTable = 1;
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}
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class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
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@ -558,6 +558,32 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
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MO.ChangeToRegister(Reg, false);
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}
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unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC)
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const {
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assert(SuperReg.isReg());
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unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
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unsigned SubReg = MRI.createVirtualRegister(SubRC);
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// Just in case the super register is itself a sub-register, copy it to a new
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// value so we don't need to wory about merging its subreg index with the
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// SubIdx passed to this function. The register coalescer should be able to
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// eliminate this extra copy.
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
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NewSuperReg)
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.addOperand(SuperReg);
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
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SubReg)
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.addReg(NewSuperReg, 0, SubIdx);
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return SubReg;
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}
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void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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@ -675,6 +701,110 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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MI->getOperand(i).setReg(DstReg);
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}
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}
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// Legalize MUBUF* instructions
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// FIXME: If we start using the non-addr64 instructions for compute, we
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// may need to legalize them here.
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int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::srsrc);
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int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::vaddr);
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if (SRsrcIdx != -1 && VAddrIdx != -1) {
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const TargetRegisterClass *VAddrRC =
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RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
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if(VAddrRC->getSize() == 8 &&
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MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
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// We have a MUBUF instruction that uses a 64-bit vaddr register and
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// srsrc has the incorrect register class. In order to fix this, we
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// need to extract the pointer from the resource descriptor (srsrc),
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// add it to the value of vadd, then store the result in the vaddr
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// operand. Then, we need to set the pointer field of the resource
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// descriptor to zero.
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MachineBasicBlock &MBB = *MI->getParent();
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MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
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MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
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unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
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unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
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unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
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// SRsrcPtrLo = srsrc:sub0
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SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
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&AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
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// SRsrcPtrHi = srsrc:sub1
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SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
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&AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
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// VAddrLo = vaddr:sub0
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VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
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&AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
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// VAddrHi = vaddr:sub1
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VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
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&AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
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// NewVaddrLo = SRsrcPtrLo + VAddrLo
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
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NewVAddrLo)
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.addReg(SRsrcPtrLo)
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.addReg(VAddrLo)
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.addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
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// NewVaddrHi = SRsrcPtrHi + VAddrHi
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
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NewVAddrHi)
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.addReg(SRsrcPtrHi)
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.addReg(VAddrHi)
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.addReg(AMDGPU::VCC, RegState::ImplicitDefine)
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.addReg(AMDGPU::VCC, RegState::Implicit);
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// NewVaddr = {NewVaddrHi, NewVaddrLo}
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
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NewVAddr)
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.addReg(NewVAddrLo)
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.addImm(AMDGPU::sub0)
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.addReg(NewVAddrHi)
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.addImm(AMDGPU::sub1);
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// Zero64 = 0
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
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Zero64)
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.addImm(0);
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// SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
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SRsrcFormatLo)
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.addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
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// SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
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SRsrcFormatHi)
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.addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
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// NewSRsrc = {Zero64, SRsrcFormat}
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BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
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NewSRsrc)
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.addReg(Zero64)
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.addImm(AMDGPU::sub0_sub1)
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.addReg(SRsrcFormatLo)
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.addImm(AMDGPU::sub2)
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.addReg(SRsrcFormatHi)
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.addImm(AMDGPU::sub3);
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// Update the instruction to use NewVaddr
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MI->getOperand(VAddrIdx).setReg(NewVAddr);
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// Update the instruction to use NewSRsrc
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MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
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}
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}
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}
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void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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@ -731,8 +861,12 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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}
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unsigned NewOpcode = getVALUOp(*Inst);
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if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
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if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
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// We cannot move this instruction to the VALU, so we should try to
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// legalize its operands instead.
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legalizeOperands(Inst);
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continue;
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}
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// Use the new VALU Opcode.
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const MCInstrDesc &NewDesc = get(NewOpcode);
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@ -25,6 +25,13 @@ class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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@ -142,6 +149,9 @@ namespace AMDGPU {
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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} // End namespace AMDGPU
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} // End namespace llvm
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
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; In this test both the pointer and the offset operands to the
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; BUFFER_LOAD instructions end up being stored in vgprs. This
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@ -8,8 +8,14 @@
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; (low 64-bits of srsrc).
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; CHECK-LABEL: @mubuf
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; Make sure we aren't using VGPRs for the source operand of S_MOV_B64
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; CHECK-NOT: S_MOV_B64 s[{{[0-9]+:[0-9]+}}], v
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; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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; instructions
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; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
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; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
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define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #1
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