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Add an ARM RSCrr instruction for disassembly only.

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Partial fix for PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-05 18:59:36 +00:00
parent 280f96c508
commit a1d410d512
2 changed files with 12 additions and 0 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1673,6 +1673,14 @@ def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
Requires<[IsARM]> {
let Inst{25} = 1;
}
// The reg/reg form is only defined for the disassembler; for codegen it is
// equivalent to SUBrr.
def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b",
[/* For disassembly only; pattern left blank */]> {
let Inst{25} = 0;
let Inst{11-4} = 0b00000000;
}
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
[(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,

4
test/MC/Disassembler/arm-tests.txt
View File

@ -65,6 +65,10 @@
# CHECK: rsbeq r0, r2, r0
0x00 0x00 0x62 0x00
# CHECK-NOT: rsceqs r0, r0, r1, lsl #0
# CHECK: rsceqs r0, r0, r1
0x01 0x00 0xf0 0x00
# CHECK: sbcs r0, pc, #1
0x01 0x00 0xdf 0xe2