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fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into: _test1: slwi r2, r4, 4 add r2, r2, r3 lwz r3, 36(r2) blr _test2: mulli r2, r4, 5 add r2, r2, r3 lbz r2, 11(r2) extsb r3, r2 blr instead of: _test1: addi r2, r4, 2 slwi r2, r2, 4 add r2, r3, r2 lwz r3, 4(r2) blr _test2: addi r2, r4, 2 mulli r2, r2, 5 add r2, r3, r2 lbz r2, 1(r2) extsb r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26535 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -802,7 +802,13 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
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return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
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}
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}
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// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
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if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
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isa<ConstantSDNode>(N0.getOperand(1))) {
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return DAG.getNode(ISD::ADD, VT,
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DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
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DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
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}
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// reassociate mul
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SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
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@ -1446,6 +1452,13 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
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if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
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return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
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DAG.getConstant(~0ULL << N1C->getValue(), VT));
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// fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
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if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
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isa<ConstantSDNode>(N0.getOperand(1))) {
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return DAG.getNode(ISD::ADD, VT,
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DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
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DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
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}
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return SDOperand();
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}
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