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Fix SROA to avoid unnecessary scalar conversions for 1-element vectors.
When a 1-element vector alloca is promoted, a store instruction can often be rewritten without converting the value to a scalar and using an insertelement instruction to stuff it into the new alloca. This patch just adds a check to skip that conversion when it is unnecessary. This turns out to be really important for some ARM Neon operations where <1 x i64> is used to get around the fact that i64 is not a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184870 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2591,22 +2591,23 @@ private:
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bool rewriteVectorizedStoreInst(Value *V,
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StoreInst &SI, Value *OldOp) {
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unsigned BeginIndex = getIndex(BeginOffset);
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unsigned EndIndex = getIndex(EndOffset);
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assert(EndIndex > BeginIndex && "Empty vector!");
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unsigned NumElements = EndIndex - BeginIndex;
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assert(NumElements <= VecTy->getNumElements() && "Too many elements!");
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Type *PartitionTy
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= (NumElements == 1) ? ElementTy
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: VectorType::get(ElementTy, NumElements);
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if (V->getType() != PartitionTy)
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V = convertValue(TD, IRB, V, PartitionTy);
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// Mix in the existing elements.
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Value *Old = IRB.CreateAlignedLoad(&NewAI, NewAI.getAlignment(),
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"load");
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V = insertVector(IRB, Old, V, BeginIndex, "vec");
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if (V->getType() != VecTy) {
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unsigned BeginIndex = getIndex(BeginOffset);
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unsigned EndIndex = getIndex(EndOffset);
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assert(EndIndex > BeginIndex && "Empty vector!");
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unsigned NumElements = EndIndex - BeginIndex;
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assert(NumElements <= VecTy->getNumElements() && "Too many elements!");
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Type *PartitionTy
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= (NumElements == 1) ? ElementTy
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: VectorType::get(ElementTy, NumElements);
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if (V->getType() != PartitionTy)
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V = convertValue(TD, IRB, V, PartitionTy);
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// Mix in the existing elements.
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Value *Old = IRB.CreateAlignedLoad(&NewAI, NewAI.getAlignment(),
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"load");
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V = insertVector(IRB, Old, V, BeginIndex, "vec");
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}
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StoreInst *Store = IRB.CreateAlignedStore(V, &NewAI, NewAI.getAlignment());
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Pass.DeadInsts.insert(&SI);
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@ -111,3 +111,27 @@ entry:
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; CHECK-NOT: alloca
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; CHECK: and i192
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}
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; When promoting an alloca to a 1-element vector type, instructions that
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; produce that same vector type should not be changed to insert one element
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; into a new vector. <rdar://problem/14249078>
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define <1 x i64> @test8(<1 x i64> %a) {
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entry:
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%a.addr = alloca <1 x i64>, align 8
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%__a = alloca <1 x i64>, align 8
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%tmp = alloca <1 x i64>, align 8
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store <1 x i64> %a, <1 x i64>* %a.addr, align 8
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%0 = load <1 x i64>* %a.addr, align 8
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store <1 x i64> %0, <1 x i64>* %__a, align 8
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%1 = load <1 x i64>* %__a, align 8
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%2 = bitcast <1 x i64> %1 to <8 x i8>
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%3 = bitcast <8 x i8> %2 to <1 x i64>
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%vshl_n = shl <1 x i64> %3, <i64 4>
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store <1 x i64> %vshl_n, <1 x i64>* %tmp
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%4 = load <1 x i64>* %tmp
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ret <1 x i64> %4
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; CHECK: @test8
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; CHECK-NOT: alloca
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; CHECK-NOT: insertelement
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; CHECK: ret <1 x i64>
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}
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