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[mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
0880939a59
commit
a1fe9ef62e
@ -114,6 +114,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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MipsAsmParser::OperandMatchResultTy
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parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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MipsAsmParser::OperandMatchResultTy
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parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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unsigned RegKind);
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@ -223,7 +226,8 @@ public:
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Kind_FGR64Regs,
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Kind_AFGR64Regs,
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Kind_CCRRegs,
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Kind_FCCRegs
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Kind_FCCRegs,
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Kind_ACRegsDSP
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};
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private:
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@ -410,6 +414,10 @@ public:
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return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
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}
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bool isACRegsDSPAsm() const {
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return Kind == k_Register && Reg.Kind == Kind_ACRegsDSP;
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const {
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return StartLoc;
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@ -1272,7 +1280,8 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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return MatchOperand_NoMatch;
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Parser.Lex(); // Eat $
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if (!tryParseRegisterOperand(Operands, isMips64())) {
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if (!tryParseRegisterOperand(Operands,
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RegKind == MipsOperand::Kind_CPU64Regs)) {
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// Set the proper register kind.
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MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
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op->setRegKind(Kind);
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@ -1367,6 +1376,39 @@ MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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}
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// If the first token is not '$' we have an error.
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if (Parser.getTok().isNot(AsmToken::Dollar))
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return MatchOperand_NoMatch;
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the '$'
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const AsmToken &Tok = Parser.getTok(); // Get next token.
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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if (!Tok.getIdentifier().startswith("acc"))
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return MatchOperand_NoMatch;
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StringRef NumString = Tok.getIdentifier().substr(3);
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unsigned IntVal;
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if (NumString.getAsInteger(10, IntVal))
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return MatchOperand_NoMatch;
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unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACRegsDSPRegClassID);
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MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
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Op->setRegKind(MipsOperand::Kind_ACRegsDSP);
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Operands.push_back(Op);
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Parser.Lex(); // Eat the register number.
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return MatchOperand_Success;
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}
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bool MipsAsmParser::searchSymbolAlias(
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SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {
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@ -250,6 +250,12 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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case Mips::BC1F:
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// bc1f $fcc0, $L1 => bc1f $L1
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return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
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case Mips::JALR:
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// jalr $ra, $r1 => jalr $r1
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return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
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case Mips::JALR64:
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// jalr $ra, $r1 => jalr $r1
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return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
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case Mips::OR:
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// or $r0, $r1, $zero => move $r0, $r1
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return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
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@ -4,9 +4,9 @@ let isCodeGenOnly = 1 in {
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ADDI_FM_MM<0xc>;
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def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>,
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ADDI_FM_MM<0x4>;
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegsOpnd>,
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegsOpnd>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd>,
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ADDI_FM_MM<0x34>;
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@ -14,7 +14,7 @@ let isCodeGenOnly = 1 in {
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM_MM;
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def LUi_MM : MMRel, LoadUpper<"lui", CPURegsOpnd, uimm16>, LUI_FM_MM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", CPURegsOpnd>, ADD_FM_MM<0, 0x150>;
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@ -22,8 +22,8 @@ let isCodeGenOnly = 1 in {
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def MUL_MM : MMRel, ArithLogicR<"mul", CPURegsOpnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM_MM<0, 0x190>;
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, CPURegs>,
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, CPURegsOpnd>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, CPURegsOpnd>,
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ADD_FM_MM<0, 0x390>;
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def AND_MM : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
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ADD_FM_MM<0, 0x250>;
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@ -56,12 +56,12 @@ let isCodeGenOnly = 1 in {
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SRLV_FM_MM<0xd0, 0>;
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/// Load and Store Instructions - aligned
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defm LB_MM : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM_MM<0x7>;
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defm LBu_MM : LoadM<"lbu", CPURegs, zextloadi8>, MMRel, LW_FM_MM<0x5>;
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defm LH_MM : LoadM<"lh", CPURegs, sextloadi16>, MMRel, LW_FM_MM<0xf>;
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defm LHu_MM : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM_MM<0xd>;
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defm LW_MM : LoadM<"lw", CPURegs>, MMRel, LW_FM_MM<0x3f>;
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defm SB_MM : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM_MM<0x6>;
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defm SH_MM : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM_MM<0xe>;
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defm SW_MM : StoreM<"sw", CPURegs>, MMRel, LW_FM_MM<0x3e>;
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defm LB_MM : LoadM<"lb", CPURegsOpnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
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defm LBu_MM : LoadM<"lbu", CPURegsOpnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
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defm LH_MM : LoadM<"lh", CPURegsOpnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
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defm LHu_MM : LoadM<"lhu", CPURegsOpnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
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defm LW_MM : LoadM<"lw", CPURegsOpnd>, MMRel, LW_FM_MM<0x3f>;
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defm SB_MM : StoreM<"sb", CPURegsOpnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
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defm SH_MM : StoreM<"sh", CPURegsOpnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
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defm SW_MM : StoreM<"sw", CPURegsOpnd>, MMRel, LW_FM_MM<0x3e>;
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}
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@ -75,9 +75,9 @@ def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
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immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64RegsOpnd>,
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SLTI_FM<0xa>;
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64RegsOpnd>,
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SLTI_FM<0xb>;
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def ANDi64 : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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and>,
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@ -88,7 +88,7 @@ def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
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xor>,
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ADDI_FM<0xe>;
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def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
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def LUi64 : LoadUpper<"lui", CPU64RegsOpnd, uimm16_64>, LUI_FM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
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@ -96,8 +96,8 @@ def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
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ADD_FM<0, 0x2d>;
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def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
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ADD_FM<0, 0x2f>;
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def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
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def SLT64 : SetCC_R<"slt", setlt, CPU64RegsOpnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, CPU64RegsOpnd>, ADD_FM<0, 0x2b>;
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def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
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@ -129,28 +129,28 @@ let Predicates = [HasMips64r2, HasStdEnc],
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let DecoderNamespace = "Mips64" in {
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/// Load and Store Instructions
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/// aligned
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defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>;
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defm LB64 : LoadM<"lb", CPU64RegsOpnd, sextloadi8, IILoad>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64RegsOpnd, zextloadi8, IILoad>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64RegsOpnd, sextloadi16, IILoad>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64RegsOpnd, zextloadi16, IILoad>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64RegsOpnd, sextloadi32, IILoad>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64RegsOpnd, zextloadi32, IILoad>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64RegsOpnd, truncstorei8, IIStore>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64RegsOpnd, truncstorei16, IIStore>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64RegsOpnd, truncstorei32, IIStore>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64RegsOpnd, load, IILoad>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64RegsOpnd, store, IIStore>, LW_FM<0x3f>;
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/// load/store left/right
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
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defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
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defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
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defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64RegsOpnd>, LW_FM<0x22>;
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defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64RegsOpnd>, LW_FM<0x26>;
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defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64RegsOpnd>, LW_FM<0x2a>;
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defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64RegsOpnd>, LW_FM<0x2e>;
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defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
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defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
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defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
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defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
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defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64RegsOpnd>, LW_FM<0x1a>;
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defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64RegsOpnd>, LW_FM<0x1b>;
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defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64RegsOpnd>, LW_FM<0x2c>;
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defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64RegsOpnd>, LW_FM<0x2d>;
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/// Load-linked, Store-conditional
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let Predicates = [NotN64, HasStdEnc] in {
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@ -164,7 +164,7 @@ let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
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}
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/// Jump and Branch Instructions
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def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
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def JR64 : IndirectBranch<CPU64RegsOpnd>, MTLO_FM<8>;
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def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>;
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@ -172,10 +172,13 @@ def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>;
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def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>;
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}
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let DecoderNamespace = "Mips64" in
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def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64", isCodeGenOnly = 1 in {
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def JALR64 : JumpLinkReg<"jalr", CPU64RegsOpnd>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<CPU64RegsOpnd, JALR, RA, CPURegsOpnd>;
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}
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def TAILCALL64_R : JumpFR<CPU64RegsOpnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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/// Multiply and Divide Instructions.
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@ -194,14 +197,14 @@ def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
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IIIdiv, 0, 1, 1>;
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def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
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def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
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def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
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def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
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def MTHI64 : MoveToLOHI<"mthi", CPU64RegsOpnd, [HI64]>, MTLO_FM<0x11>;
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def MTLO64 : MoveToLOHI<"mtlo", CPU64RegsOpnd, [LO64]>, MTLO_FM<0x13>;
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def MFHI64 : MoveFromLOHI<"mfhi", CPU64RegsOpnd, [HI64]>, MFLO_FM<0x10>;
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def MFLO64 : MoveFromLOHI<"mflo", CPU64RegsOpnd, [LO64]>, MFLO_FM<0x12>;
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/// Sign Ext In Register Instructions.
|
||||
def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
|
||||
def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
|
||||
def SEB64 : SignExtInReg<"seb", i8, CPU64RegsOpnd>, SEB_FM<0x10, 0x20>;
|
||||
def SEH64 : SignExtInReg<"seh", i16, CPU64RegsOpnd>, SEB_FM<0x18, 0x20>;
|
||||
|
||||
/// Count Leading
|
||||
def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
|
||||
@ -211,11 +214,11 @@ def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
|
||||
def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
|
||||
def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
|
||||
|
||||
def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
|
||||
def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64RegsOpnd, mem_ea_64>, LW_FM<0x19>;
|
||||
|
||||
}
|
||||
let DecoderNamespace = "Mips64" in {
|
||||
def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
|
||||
def RDHWR64 : ReadHardware<CPU64RegsOpnd, HW64RegsOpnd>, RDHWR_FM;
|
||||
|
||||
def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
|
||||
let Pattern = []<dag> in {
|
||||
@ -336,7 +339,7 @@ def : InstAlias<"and $rs, $rt, $imm",
|
||||
1>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"slt $rs, $rt, $imm",
|
||||
(SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
|
||||
(SLTi64 CPURegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"xor $rs, $rt, $imm",
|
||||
(XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
|
||||
@ -345,13 +348,7 @@ def : InstAlias<"xor $rs, $rt, $imm",
|
||||
def : InstAlias<"not $rt, $rs",
|
||||
(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
|
||||
def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
|
||||
Requires<[HasMips64]>;
|
||||
def : InstAlias<"j $rs", (JR64 CPU64RegsOpnd:$rs), 0>, Requires<[HasMips64]>;
|
||||
def : InstAlias<"daddu $rs, $rt, $imm",
|
||||
(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
|
||||
1>;
|
||||
|
||||
@ -1242,8 +1242,8 @@ def PREPEND : PREPEND_ENC, PREPEND_DESC;
|
||||
// Pseudos.
|
||||
let isPseudo = 1 in {
|
||||
// Pseudo instructions for loading and storing accumulator registers.
|
||||
defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSP>;
|
||||
defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
|
||||
defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSPOpnd>;
|
||||
defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSPOpnd>;
|
||||
|
||||
// Pseudos for loading and storing ccond field of DSP control register.
|
||||
defm LOAD_CCOND_DSP : LoadM<"load_ccond_dsp", DSPCC>;
|
||||
|
||||
@ -411,30 +411,30 @@ class MArithR<string opstr, bit isComm = 0> :
|
||||
}
|
||||
|
||||
// Logical
|
||||
class LogicNOR<string opstr, RegisterOperand RC>:
|
||||
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
|
||||
class LogicNOR<string opstr, RegisterOperand RO>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
|
||||
!strconcat(opstr, "\t$rd, $rs, $rt"),
|
||||
[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIArith, FrmR, opstr> {
|
||||
[(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
|
||||
let isCommutable = 1;
|
||||
}
|
||||
|
||||
// Shifts
|
||||
class shift_rotate_imm<string opstr, Operand ImmOpnd,
|
||||
RegisterOperand RC, SDPatternOperator OpNode = null_frag,
|
||||
RegisterOperand RO, SDPatternOperator OpNode = null_frag,
|
||||
SDPatternOperator PF = null_frag> :
|
||||
InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
|
||||
InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
|
||||
!strconcat(opstr, "\t$rd, $rt, $shamt"),
|
||||
[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
|
||||
[(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
|
||||
|
||||
class shift_rotate_reg<string opstr, RegisterOperand RC,
|
||||
class shift_rotate_reg<string opstr, RegisterOperand RO,
|
||||
SDPatternOperator OpNode = null_frag>:
|
||||
InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs),
|
||||
InstSE<(outs RO:$rd), (ins RO:$rt, CPURegsOpnd:$rs),
|
||||
!strconcat(opstr, "\t$rd, $rt, $rs"),
|
||||
[(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIArith, FrmR, opstr>;
|
||||
[(set RO:$rd, (OpNode RO:$rt, CPURegsOpnd:$rs))], IIArith, FrmR, opstr>;
|
||||
|
||||
// Load Upper Imediate
|
||||
class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
|
||||
InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
|
||||
class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
|
||||
InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
|
||||
[], IIArith, FrmI>, IsAsCheapAsAMove {
|
||||
let neverHasSideEffects = 1;
|
||||
let isReMaterializable = 1;
|
||||
@ -449,47 +449,47 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
}
|
||||
|
||||
// Memory Load/Store
|
||||
class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
|
||||
class Load<string opstr, SDPatternOperator OpNode, DAGOperand RO,
|
||||
InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
|
||||
string ofsuffix> :
|
||||
InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
|
||||
InstSE<(outs RO:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
|
||||
!strconcat(opstr, ofsuffix)> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
let canFoldAsLoad = 1;
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
|
||||
class Store<string opstr, SDPatternOperator OpNode, DAGOperand RO,
|
||||
InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
|
||||
string ofsuffix> :
|
||||
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
|
||||
InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI,
|
||||
!strconcat(opstr, ofsuffix)> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
let mayStore = 1;
|
||||
}
|
||||
|
||||
multiclass LoadM<string opstr, RegisterClass RC,
|
||||
multiclass LoadM<string opstr, DAGOperand RO,
|
||||
SDPatternOperator OpNode = null_frag,
|
||||
InstrItinClass Itin = NoItinerary,
|
||||
ComplexPattern Addr = addr> {
|
||||
def NAME : Load<opstr, OpNode, RC, Itin, mem, Addr, "">,
|
||||
def NAME : Load<opstr, OpNode, RO, Itin, mem, Addr, "">,
|
||||
Requires<[NotN64, HasStdEnc]>;
|
||||
def _P8 : Load<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
|
||||
def _P8 : Load<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
|
||||
Requires<[IsN64, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass StoreM<string opstr, RegisterClass RC,
|
||||
multiclass StoreM<string opstr, DAGOperand RO,
|
||||
SDPatternOperator OpNode = null_frag,
|
||||
InstrItinClass Itin = NoItinerary,
|
||||
ComplexPattern Addr = addr> {
|
||||
def NAME : Store<opstr, OpNode, RC, Itin, mem, Addr, "">,
|
||||
def NAME : Store<opstr, OpNode, RO, Itin, mem, Addr, "">,
|
||||
Requires<[NotN64, HasStdEnc]>;
|
||||
def _P8 : Store<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
|
||||
def _P8 : Store<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
|
||||
Requires<[IsN64, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
@ -498,36 +498,36 @@ multiclass StoreM<string opstr, RegisterClass RC,
|
||||
|
||||
// Load/Store Left/Right
|
||||
let canFoldAsLoad = 1 in
|
||||
class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
|
||||
class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
|
||||
Operand MemOpnd> :
|
||||
InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
|
||||
InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
|
||||
!strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
|
||||
[(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
string Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
|
||||
class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
|
||||
Operand MemOpnd>:
|
||||
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
|
||||
InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
|
||||
let DecoderMethod = "DecodeMem";
|
||||
}
|
||||
|
||||
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
|
||||
def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
|
||||
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
|
||||
def NAME : LoadLeftRight<opstr, OpNode, RO, mem>,
|
||||
Requires<[NotN64, HasStdEnc]>;
|
||||
def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
|
||||
def _P8 : LoadLeftRight<opstr, OpNode, RO, mem64>,
|
||||
Requires<[IsN64, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
|
||||
def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
|
||||
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
|
||||
def NAME : StoreLeftRight<opstr, OpNode, RO, mem>,
|
||||
Requires<[NotN64, HasStdEnc]>;
|
||||
def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
|
||||
def _P8 : StoreLeftRight<opstr, OpNode, RO, mem64>,
|
||||
Requires<[IsN64, HasStdEnc]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
@ -535,10 +535,10 @@ multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
|
||||
}
|
||||
|
||||
// Conditional Branch
|
||||
class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
|
||||
InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
|
||||
class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
|
||||
InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
|
||||
!strconcat(opstr, "\t$rs, $rt, $offset"),
|
||||
[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
|
||||
[(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
|
||||
FrmI> {
|
||||
let isBranch = 1;
|
||||
let isTerminator = 1;
|
||||
@ -546,10 +546,10 @@ class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
|
||||
let Defs = [AT];
|
||||
}
|
||||
|
||||
class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
|
||||
InstSE<(outs), (ins RC:$rs, brtarget:$offset),
|
||||
class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
|
||||
InstSE<(outs), (ins RO:$rs, brtarget:$offset),
|
||||
!strconcat(opstr, "\t$rs, $offset"),
|
||||
[(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
|
||||
[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
|
||||
let isBranch = 1;
|
||||
let isTerminator = 1;
|
||||
let hasDelaySlot = 1;
|
||||
@ -557,17 +557,17 @@ class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
|
||||
}
|
||||
|
||||
// SetCC
|
||||
class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
|
||||
InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
|
||||
class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
|
||||
InstSE<(outs CPURegsOpnd:$rd), (ins RO:$rs, RO:$rt),
|
||||
!strconcat(opstr, "\t$rd, $rs, $rt"),
|
||||
[(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
|
||||
[(set CPURegsOpnd:$rd, (cond_op RO:$rs, RO:$rt))],
|
||||
IIslt, FrmR, opstr>;
|
||||
|
||||
class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
|
||||
RegisterClass RC>:
|
||||
InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
|
||||
RegisterOperand RO>:
|
||||
InstSE<(outs CPURegsOpnd:$rt), (ins RO:$rs, Od:$imm16),
|
||||
!strconcat(opstr, "\t$rt, $rs, $imm16"),
|
||||
[(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
|
||||
[(set CPURegsOpnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
|
||||
IIslt, FrmI, opstr>;
|
||||
|
||||
// Jump
|
||||
@ -596,17 +596,17 @@ class UncondBranch<string opstr> :
|
||||
|
||||
// Base class for indirect branch and return instruction classes.
|
||||
let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
|
||||
class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
|
||||
InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
|
||||
class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
|
||||
InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
|
||||
|
||||
// Indirect branch
|
||||
class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
|
||||
class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
|
||||
let isBranch = 1;
|
||||
let isIndirectBranch = 1;
|
||||
}
|
||||
|
||||
// Return instruction
|
||||
class RetBase<RegisterClass RC>: JumpFR<RC> {
|
||||
class RetBase<RegisterOperand RO>: JumpFR<RO> {
|
||||
let isReturn = 1;
|
||||
let isCodeGenOnly = 1;
|
||||
let hasCtrlDep = 1;
|
||||
@ -621,13 +621,13 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in {
|
||||
let DecoderMethod = "DecodeJumpTarget";
|
||||
}
|
||||
|
||||
class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
|
||||
Register RetReg>:
|
||||
PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
|
||||
PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
|
||||
class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
|
||||
Register RetReg, RegisterOperand ResRO = RO>:
|
||||
PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
|
||||
PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
|
||||
|
||||
class JumpLinkReg<string opstr, RegisterClass RC>:
|
||||
InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
class JumpLinkReg<string opstr, RegisterOperand RO>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
[], IIBranch, FrmR>;
|
||||
|
||||
class BGEZAL_FT<string opstr, RegisterOperand RO> :
|
||||
@ -715,21 +715,21 @@ class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
|
||||
}
|
||||
|
||||
// Move from Hi/Lo
|
||||
class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
|
||||
InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
|
||||
class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
|
||||
InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
|
||||
let Uses = UseRegs;
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
|
||||
InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
|
||||
class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
|
||||
InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
|
||||
let Defs = DefRegs;
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
|
||||
InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
|
||||
class EffectiveAddress<string opstr, RegisterOperand RO, Operand Mem> :
|
||||
InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
|
||||
[(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
|
||||
let isCodeGenOnly = 1;
|
||||
let DecoderMethod = "DecodeMem";
|
||||
}
|
||||
@ -747,9 +747,9 @@ class CountLeading1<string opstr, RegisterOperand RO>:
|
||||
|
||||
|
||||
// Sign Extend in Register.
|
||||
class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
|
||||
InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
|
||||
[(set RC:$rd, (sext_inreg RC:$rt, vt))], IIseb, FrmR> {
|
||||
class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
|
||||
[(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
|
||||
let Predicates = [HasSEInReg, HasStdEnc];
|
||||
}
|
||||
|
||||
@ -762,8 +762,8 @@ class SubwordSwap<string opstr, RegisterOperand RO>:
|
||||
}
|
||||
|
||||
// Read Hardware
|
||||
class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
|
||||
InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
|
||||
class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
|
||||
InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
|
||||
IIArith, FrmR>;
|
||||
|
||||
// Ext and Ins
|
||||
@ -891,9 +891,9 @@ def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, IIArith, immSExt16,
|
||||
add>,
|
||||
ADDI_FM<0x9>, IsAsCheapAsAMove;
|
||||
def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
|
||||
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
|
||||
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegsOpnd>,
|
||||
SLTI_FM<0xa>;
|
||||
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
|
||||
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegsOpnd>,
|
||||
SLTI_FM<0xb>;
|
||||
def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, IILogic, immZExt16,
|
||||
and>,
|
||||
@ -904,7 +904,7 @@ def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, IILogic, immZExt16,
|
||||
def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, IILogic, immZExt16,
|
||||
xor>,
|
||||
ADDI_FM<0xe>;
|
||||
def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
|
||||
def LUi : MMRel, LoadUpper<"lui", CPURegsOpnd, uimm16>, LUI_FM;
|
||||
|
||||
/// Arithmetic Instructions (3-Operand, R-Type)
|
||||
def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIArith, add>,
|
||||
@ -915,8 +915,8 @@ def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
|
||||
ADD_FM<0x1c, 2>;
|
||||
def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
|
||||
def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
|
||||
def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
|
||||
def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
|
||||
def SLT : MMRel, SetCC_R<"slt", setlt, CPURegsOpnd>, ADD_FM<0, 0x2a>;
|
||||
def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegsOpnd>, ADD_FM<0, 0x2b>;
|
||||
def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IILogic, and>,
|
||||
ADD_FM<0, 0x24>;
|
||||
def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IILogic, or>,
|
||||
@ -947,22 +947,22 @@ let Predicates = [HasMips32r2, HasStdEnc] in {
|
||||
|
||||
/// Load and Store Instructions
|
||||
/// aligned
|
||||
defm LB : LoadM<"lb", CPURegs, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
|
||||
defm LBu : LoadM<"lbu", CPURegs, zextloadi8, IILoad, addrDefault>, MMRel,
|
||||
defm LB : LoadM<"lb", CPURegsOpnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
|
||||
defm LBu : LoadM<"lbu", CPURegsOpnd, zextloadi8, IILoad, addrDefault>, MMRel,
|
||||
LW_FM<0x24>;
|
||||
defm LH : LoadM<"lh", CPURegs, sextloadi16, IILoad, addrDefault>, MMRel,
|
||||
defm LH : LoadM<"lh", CPURegsOpnd, sextloadi16, IILoad, addrDefault>, MMRel,
|
||||
LW_FM<0x21>;
|
||||
defm LHu : LoadM<"lhu", CPURegs, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
|
||||
defm LW : LoadM<"lw", CPURegs, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
|
||||
defm SB : StoreM<"sb", CPURegs, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
|
||||
defm SH : StoreM<"sh", CPURegs, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
|
||||
defm SW : StoreM<"sw", CPURegs, store, IIStore>, MMRel, LW_FM<0x2b>;
|
||||
defm LHu : LoadM<"lhu", CPURegsOpnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
|
||||
defm LW : LoadM<"lw", CPURegsOpnd, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
|
||||
defm SB : StoreM<"sb", CPURegsOpnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
|
||||
defm SH : StoreM<"sh", CPURegsOpnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
|
||||
defm SW : StoreM<"sw", CPURegsOpnd, store, IIStore>, MMRel, LW_FM<0x2b>;
|
||||
|
||||
/// load/store left/right
|
||||
defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
|
||||
defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
|
||||
defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
|
||||
defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
|
||||
defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegsOpnd>, LW_FM<0x22>;
|
||||
defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegsOpnd>, LW_FM<0x26>;
|
||||
defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegsOpnd>, LW_FM<0x2a>;
|
||||
defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegsOpnd>, LW_FM<0x2e>;
|
||||
|
||||
def SYNC : SYNC_FT, SYNC_FM;
|
||||
def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
|
||||
@ -987,7 +987,7 @@ let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
/// Jump and Branch Instructions
|
||||
def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
|
||||
Requires<[RelocStatic, HasStdEnc]>, IsBranch;
|
||||
def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
|
||||
def JR : IndirectBranch<CPURegsOpnd>, MTLO_FM<8>;
|
||||
def B : UncondBranch<"b">, B_FM;
|
||||
def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
|
||||
def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
|
||||
@ -997,15 +997,15 @@ def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
|
||||
def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
|
||||
|
||||
def JAL : JumpLink<"jal">, FJ<3>;
|
||||
def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
|
||||
def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
|
||||
def JALR : JumpLinkReg<"jalr", CPURegsOpnd>, JALR_FM;
|
||||
def JALRPseudo : JumpLinkRegPseudo<CPURegsOpnd, JALR, RA>;
|
||||
def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
|
||||
def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
|
||||
def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
|
||||
def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
|
||||
def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
|
||||
def TAILCALL_R : JumpFR<CPURegsOpnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
|
||||
|
||||
def RET : RetBase<CPURegs>, MTLO_FM<8>;
|
||||
def RET : RetBase<CPURegsOpnd>, MTLO_FM<8>;
|
||||
|
||||
// Exception handling related node and instructions.
|
||||
// The conversion sequence is:
|
||||
@ -1042,14 +1042,14 @@ def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
|
||||
0, 1, 1>;
|
||||
|
||||
def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
|
||||
def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
|
||||
def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
|
||||
def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
|
||||
def MTHI : MoveToLOHI<"mthi", CPURegsOpnd, [HI]>, MTLO_FM<0x11>;
|
||||
def MTLO : MoveToLOHI<"mtlo", CPURegsOpnd, [LO]>, MTLO_FM<0x13>;
|
||||
def MFHI : MoveFromLOHI<"mfhi", CPURegsOpnd, [HI]>, MFLO_FM<0x10>;
|
||||
def MFLO : MoveFromLOHI<"mflo", CPURegsOpnd, [LO]>, MFLO_FM<0x12>;
|
||||
|
||||
/// Sign Ext In Register Instructions.
|
||||
def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
|
||||
def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
|
||||
def SEB : SignExtInReg<"seb", i8, CPURegsOpnd>, SEB_FM<0x10, 0x20>;
|
||||
def SEH : SignExtInReg<"seh", i16, CPURegsOpnd>, SEB_FM<0x18, 0x20>;
|
||||
|
||||
/// Count Leading
|
||||
def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
|
||||
@ -1065,7 +1065,7 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
|
||||
// instructions. The same not happens for stack address copies, so an
|
||||
// add op with mem ComplexPattern is used and the stack address copy
|
||||
// can be matched. It's similar to Sparc LEA_ADDRi
|
||||
def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
|
||||
def LEA_ADDiu : EffectiveAddress<"addiu", CPURegsOpnd, mem_ea>, LW_FM<9>;
|
||||
|
||||
// MADD*/MSUB*
|
||||
def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
|
||||
@ -1077,7 +1077,7 @@ def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
|
||||
def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
|
||||
def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
|
||||
|
||||
def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
|
||||
def RDHWR : ReadHardware<CPURegsOpnd, HWRegsOpnd>, RDHWR_FM;
|
||||
|
||||
def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
|
||||
def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
|
||||
@ -1112,12 +1112,11 @@ def : InstAlias<"add $rs, $rt, $imm",
|
||||
(ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
|
||||
def : InstAlias<"and $rs, $rt, $imm",
|
||||
(ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
|
||||
def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
|
||||
def : InstAlias<"j $rs", (JR CPURegsOpnd:$rs), 0>,
|
||||
Requires<[NotMips64]>;
|
||||
def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
|
||||
def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>;
|
||||
def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>,
|
||||
Requires<[NotMips64]>;
|
||||
def : InstAlias<"jalr $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
|
||||
def : InstAlias<"jal $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
|
||||
def : InstAlias<"jal $rd,$rs", (JALR CPURegsOpnd:$rd, CPURegsOpnd:$rs), 0>;
|
||||
def : InstAlias<"not $rt, $rs",
|
||||
(NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
|
||||
def : InstAlias<"neg $rt, $rs",
|
||||
@ -1125,7 +1124,7 @@ def : InstAlias<"neg $rt, $rs",
|
||||
def : InstAlias<"negu $rt, $rs",
|
||||
(SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
|
||||
def : InstAlias<"slt $rs, $rt, $imm",
|
||||
(SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
|
||||
(SLTi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
|
||||
def : InstAlias<"xor $rs, $rt, $imm",
|
||||
(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
|
||||
Requires<[NotMips64]>;
|
||||
|
||||
@ -345,6 +345,11 @@ def CPU64RegsAsmOperand : MipsAsmRegOperand {
|
||||
let ParserMethod = "parseCPU64Regs";
|
||||
}
|
||||
|
||||
def ACRegsDSPAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "ACRegsDSPAsm";
|
||||
let ParserMethod = "parseACRegsDSP";
|
||||
}
|
||||
|
||||
def CCRAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "CCRAsm";
|
||||
let ParserMethod = "parseCCRRegs";
|
||||
@ -414,4 +419,8 @@ def FGR32RegsOpnd : RegisterOperand<FGR32> {
|
||||
|
||||
def FCCRegsOpnd : RegisterOperand<FCC> {
|
||||
let ParserMatchClass = FCCRegsAsmOperand;
|
||||
}
|
||||
}
|
||||
|
||||
def ACRegsDSPOpnd : RegisterOperand<ACRegsDSP> {
|
||||
let ParserMatchClass = ACRegsDSPAsmOperand;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user