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MIPS DSP: ADDU.QB instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
01f7089bca
commit
a216401621
@ -29,6 +29,34 @@ class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
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let Predicates = [HasDSP];
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}
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// ADDU.QB sub-class format.
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class ADDU_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<5> rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b010000;
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}
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// DPA.W.PH sub-class format.
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class DPA_W_PH_FMT<bits<5> op> : DSPInst {
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bits<2> ac;
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@ -83,7 +83,34 @@ class UseAC {
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list<Register> Uses = [AC0];
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}
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class UseDSPCtrl {
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list<Register> Uses = [DSPCtrl];
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}
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class ClearDefs {
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list<Register> Defs = [];
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}
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// Instruction encoding.
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class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
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class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
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class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
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class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
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class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
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class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
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class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
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class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
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class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
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class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
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class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
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class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
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class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
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class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
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class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
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class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
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class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
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class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
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class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
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class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
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class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
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class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
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@ -121,6 +148,11 @@ class SHILO_ENC : SHILO_R1_FMT<0b11010>;
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class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
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class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
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class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
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class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
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class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
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class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
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class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
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class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
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class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
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class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
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@ -132,6 +164,28 @@ class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
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class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
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// Instruction desc.
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class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCD,
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RegisterClass RCS, RegisterClass RCT = RCS> {
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dag OutOperandList = (outs RCD:$rd);
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dag InOperandList = (ins RCS:$rs, RCT:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCD,
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RegisterClass RCS = RCD> {
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dag OutOperandList = (outs RCD:$rd);
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dag InOperandList = (ins RCS:$rs);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
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list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
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InstrItinClass Itinerary = itin;
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list<Register> Defs = [DSPCtrl];
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}
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class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rt);
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@ -238,7 +292,77 @@ class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
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// MIPS DSP Rev 1
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//===----------------------------------------------------------------------===//
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// Addition/subtraction
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class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable;
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class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary,
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DSPRegs, DSPRegs>;
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class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
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NoItinerary, DSPRegs, DSPRegs>;
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class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable;
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class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary,
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DSPRegs, DSPRegs>;
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class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
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NoItinerary, CPURegs, CPURegs>,
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IsCommutable;
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class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
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NoItinerary, CPURegs, CPURegs>;
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class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
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CPURegs, CPURegs>, IsCommutable;
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class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
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CPURegs, CPURegs>,
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IsCommutable, UseDSPCtrl;
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class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
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CPURegs, CPURegs>, ClearDefs;
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class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
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NoItinerary, CPURegs, DSPRegs>,
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ClearDefs;
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// Multiplication
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class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
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int_mips_muleu_s_ph_qbl,
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NoItinerary, DSPRegs, DSPRegs>;
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class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
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int_mips_muleu_s_ph_qbr,
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NoItinerary, DSPRegs, DSPRegs>;
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class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
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int_mips_muleq_s_w_phl,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
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int_mips_muleq_s_w_phr,
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NoItinerary, CPURegs, DSPRegs>,
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IsCommutable;
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class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">;
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class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">;
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@ -322,6 +446,25 @@ class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 2
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// Addition/subtraction
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class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
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DSPRegs, DSPRegs>, IsCommutable;
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class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
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DSPRegs, DSPRegs>;
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class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
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NoItinerary, DSPRegs, DSPRegs>;
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// Multiplication
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class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
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NoItinerary, DSPRegs, DSPRegs>,
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IsCommutable;
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// Dot product with accumulate/subtract
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class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">;
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@ -346,6 +489,25 @@ def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
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// Instruction defs.
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// MIPS DSP Rev 1
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def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
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def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
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def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
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def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
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def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
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def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
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def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
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def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
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def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
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def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
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def ADDSC : ADDSC_ENC, ADDSC_DESC;
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def ADDWC : ADDWC_ENC, ADDWC_DESC;
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def MODSUB : MODSUB_ENC, MODSUB_DESC;
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def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
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def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
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def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
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def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
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def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
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def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
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def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
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def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
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def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
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@ -385,6 +547,11 @@ def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
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// MIPS DSP Rev 2
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let Predicates = [HasDSPR2] in {
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def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
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def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
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def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
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def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
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def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
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def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
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def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
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def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
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@ -357,3 +357,242 @@ entry:
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}
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declare i64 @llvm.mips.multu(i32, i32) nounwind readnone
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define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: addq.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.addq.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind
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define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: addq_s.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.addq.s.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: addq_s.w
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%0 = tail call i32 @llvm.mips.addq.s.w(i32 %a0, i32 %a1)
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ret i32 %0
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}
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declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind
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define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: addu.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
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define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: addu_s.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
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define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
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entry:
|
||||
; CHECK: subq.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subq.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: subq_s.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subq.s.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
|
||||
entry:
|
||||
; CHECK: subq_s.w
|
||||
|
||||
%0 = tail call i32 @llvm.mips.subq.s.w(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: subu.qb
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1)
|
||||
%3 = bitcast <4 x i8> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: subu_s.qb
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <4 x i8>
|
||||
%2 = tail call <4 x i8> @llvm.mips.subu.s.qb(<4 x i8> %0, <4 x i8> %1)
|
||||
%3 = bitcast <4 x i8> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
|
||||
entry:
|
||||
; CHECK: addsc
|
||||
|
||||
%0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.addsc(i32, i32) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
|
||||
entry:
|
||||
; CHECK: addwc
|
||||
|
||||
%0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.addwc(i32, i32) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: modsub
|
||||
|
||||
%0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone
|
||||
|
||||
define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: raddu.w.qb
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call i32 @llvm.mips.raddu.w.qb(<4 x i8> %0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: muleu_s.ph.qbl
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: muleu_s.ph.qbr
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: mulq_rs.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: muleq_s.w.phl
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call i32 @llvm.mips.muleq.s.w.phl(<2 x i16> %0, <2 x i16> %1)
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: muleq_s.w.phr
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call i32 @llvm.mips.muleq.s.w.phr(<2 x i16> %0, <2 x i16> %1)
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
@ -107,3 +107,73 @@ entry:
|
||||
}
|
||||
|
||||
declare i64 @llvm.mips.dpsqx.sa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_addu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: addu.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.addu.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.addu.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_addu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: addu_s.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.addu.s.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.addu.s.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_mulq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: mulq_s.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_subu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: subu.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subu.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subu.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
define { i32 } @test__builtin_mips_subu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: subu_s.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = bitcast i32 %a1.coerce to <2 x i16>
|
||||
%2 = tail call <2 x i16> @llvm.mips.subu.s.ph(<2 x i16> %0, <2 x i16> %1)
|
||||
%3 = bitcast <2 x i16> %2 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.subu.s.ph(<2 x i16>, <2 x i16>) nounwind
|
||||
|
||||
Loading…
Reference in New Issue
Block a user