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[Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2014-03-02 06:28:15 +00:00
parent 18fe44cb05
commit a21b315a06
5 changed files with 156 additions and 86 deletions
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17
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@@ -68,8 +68,7 @@ class SparcAsmParser : public MCTargetAsmParser {
StringRef Name);
OperandMatchResultTy
parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false,
bool createTokenForFCC = true);
parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
OperandMatchResultTy
parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@@ -633,9 +632,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
SparcOperand *Op = 0;
bool createTokenForFCC = !(Mnemonic == "fcmps" || Mnemonic == "fcmpd"
|| Mnemonic == "fcmpq");
ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"), createTokenForFCC);
ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
if (ResTy != MatchOperand_Success || !Op)
return MatchOperand_ParseFail;
@@ -646,8 +643,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
}
SparcAsmParser::OperandMatchResultTy
SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
bool createTokenForFCC)
SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
{
SMLoc S = Parser.getTok().getLoc();
@@ -680,13 +676,6 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
else
Op = SparcOperand::CreateToken("%icc", S);
break;
case Sparc::FCC0:
if (createTokenForFCC) {
assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
Op = SparcOperand::CreateToken("%fcc0", S);
break;
}
}
break;
}